JPS59100537A - Formation of electrode wiring - Google Patents

Formation of electrode wiring

Info

Publication number
JPS59100537A
JPS59100537A JP21032082A JP21032082A JPS59100537A JP S59100537 A JPS59100537 A JP S59100537A JP 21032082 A JP21032082 A JP 21032082A JP 21032082 A JP21032082 A JP 21032082A JP S59100537 A JPS59100537 A JP S59100537A
Authority
JP
Japan
Prior art keywords
film
etching
ion
electrode wiring
ion implantation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21032082A
Other languages
Japanese (ja)
Inventor
Yorisada Kawakami
川上 頼貞
Shotaro Umebachi
梅鉢 昭太郎
Takeshi Umegaki
梅垣 武士
Tsuneo Yamaguchi
恒夫 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP21032082A priority Critical patent/JPS59100537A/en
Publication of JPS59100537A publication Critical patent/JPS59100537A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To perform an etching that influences by aluminum oxidized layers on the surface of an Al film have been removed by a method wherein an ion implantation treatment is performed on metal films including aluminum, and, after that, a dry etching is performed. CONSTITUTION:An SiO2 film 2 is formed on a semiconductor substrate 1. An Al film 3 is coated on the SiO2 film 2. Photoresist films 4 are provided on the Al film 3 for forming the prescribed pattern. An ion current is exposed to the photoresist films 4 and the Al film 3 exposed at the pattern apertures thereof and an ion implantation is performed. Then, a reactive ion etching is performed using carbon tetrachloride as the etching gas.

Description

【発明の詳細な説明】 産業上の利用分野 この発明は微細な電極配線パターンに金属膜をエツチン
グ形成する電極配線形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to a method for forming electrode wiring by etching a metal film into a fine electrode wiring pattern.

従来例の構成とその問題点 たとえば、半導体装置の電極配線は、所定半導体基板表
面にアルミニウム(Al)膜あるいはアルミニウム合金
膜(以下、単にM膜と略す)を形成L、コh−trハク
ー二/グされたフォトレジスト膜マスクに忠実にエツチ
ング処理して所望形状に加工形成される。そして、この
エツチング処理に、近頃、ドライエツチング法と称して
、化学的不活性イオン捷たは化学的活性イオンを被エツ
チング処理体面に垂直な方向に突入させてエツチングを
行なうイオンエツチング法が用いられるようになってき
た。わけても、化学的活性イオンを用いる、いわゆるリ
アクティブイオンエツチング法はAl膜の微細加工に好
適で、半導体装置の電極配線形成方法にしばしば利用さ
れている。ところが、Al膜は表面に薄いアルミニウム
酸化層(A1203)を形成し易く、たとえば、室温で
もA7膜を空気にさらすと、その表面が酸化層に転化す
ることは衆知であシ、まだ、このアルミニウム酸化層は
、A7膜とに1異なり、イオンエツチングに耐性がある
。加えてAβ膜上のアルミニウム酸化層は数十オングス
トロームの厚みのばらつきがあり、この厚みのシ;1−
らつきがイオンエツチングにおけるエツチング速度のば
らつきにもなり、従来、これが、たとえば、・・ソチ処
理方式でイオンエツチングを行なつ/こときのウェハ間
のエツチング速度の不均一性を生み出していた。
Conventional Structures and Problems Therefor, for example, the electrode wiring of a semiconductor device is formed by forming an aluminum (Al) film or an aluminum alloy film (hereinafter simply referred to as M film) on the surface of a predetermined semiconductor substrate. A desired shape is formed by etching the photoresist film mask faithfully. Recently, an ion etching method called a dry etching method has been used for this etching process, in which chemically inactive ions or chemically active ions are injected in a direction perpendicular to the surface of the object to be etched. It's starting to look like this. In particular, the so-called reactive ion etching method, which uses chemically active ions, is suitable for microfabrication of Al films, and is often used as a method for forming electrode wiring in semiconductor devices. However, it is well known that Al films tend to form a thin aluminum oxide layer (A1203) on the surface. For example, it is well known that when an A7 film is exposed to air even at room temperature, the surface converts into an oxide layer. The oxide layer differs from the A7 film in that it is resistant to ion etching. In addition, the thickness of the aluminum oxide layer on the Aβ film varies by several tens of angstroms;
Wobble also causes variations in the etching rate in ion etching, and in the past, this has caused non-uniformity in etching rate between wafers, for example, when ion etching is performed using the Sochi process.

さらに、Al膜と通常のフォトレジスト膜とはエツチン
グ速度比が小さく、高精度微細パターンの加工には多く
の難点があった。
Furthermore, the etching rate ratio between the Al film and the ordinary photoresist film is small, and there are many difficulties in processing fine patterns with high precision.

発明の目的 本発明は、Al膜の均一なエツチングを可能にんずとと
もに、Al膜とフォトレジスト膜とのエツチング速度比
をも大幅に改善することができる電1;メ配線形成方法
を提供するものである。
OBJECTS OF THE INVENTION The present invention provides a method for forming electrical wiring, which not only enables uniform etching of an Al film, but also greatly improves the etching rate ratio between the Al film and the photoresist film. It is something.

発明の構成 不発明は、要約するに、アルミニウムを含む金属膜にイ
オン注入処理を施しだ後、イオンエツチングを行々う工
程を有するものであり、これによれば、Al膜の表面が
イオン衝撃を受けて、エツチング速度が増大し、エツチ
ングが容易になる。
Components of the Invention In summary, the invention includes a step of performing ion etching after ion implantation into a metal film containing aluminum. According to this, the surface of the Al film is exposed to ion bombardment. As a result, the etching speed increases and etching becomes easier.

実施例の説明 第1図〜第4図は本発明の実施例で、半導体装置の製造
工程順の断面図である。第1図で、半導体基板1上に二
酸化シリコン(Si02)膜2を熱酸化法あるいは化学
的蒸着法(以下、CVD法と呼ぶ)により形成する。次
に、第2図で前記5102膜2の上に、Al膜3を被着
する。人l膜3は、電極用のアルミニウムのほか、A、
l −3i、 )、l −3i −Cuなど、一般に使
用されるアルミニウムの合金膜が利用可能である。つい
で、第3図のように、前記kll膜上上フォトレジスト
膜4を設け、これを周知のフォトリングラフィ技術によ
り所望パターンに形成する。そして、第4図で、前記フ
ォトレジスト膜4およびそのパターン開孔部に露出しr
r)lt膜3にイオン流5を当て、イオン注入を行なう
。イオン注入の条件は、例えばボロンのイオンヲ、加速
電圧5oKeV、  ドース量5x1o”イ、tz%4
で実行した。なお、イオン注入(打込み)の条件(弓1
、l1人イオンをボロノフ リン、アルコ゛ン、シリコ
ンから選定したとさ、注入量を3X1015〜3×10
15イオン/Ca +加速電圧をs c) KeV以下
で最適設定が可能であった。
DESCRIPTION OF EMBODIMENTS FIGS. 1 to 4 show embodiments of the present invention, and are sectional views showing the steps of manufacturing a semiconductor device. In FIG. 1, a silicon dioxide (Si02) film 2 is formed on a semiconductor substrate 1 by a thermal oxidation method or a chemical vapor deposition method (hereinafter referred to as CVD method). Next, as shown in FIG. 2, an Al film 3 is deposited on the 5102 film 2. In addition to aluminum for electrodes, the human membrane 3 is made of A,
Commonly used aluminum alloy films such as l-3i, ) and l-3i-Cu can be used. Next, as shown in FIG. 3, a photoresist film 4 is provided on the KLL film, and is formed into a desired pattern by a well-known photolithography technique. In FIG. 4, the photoresist film 4 and its pattern openings are exposed.
r) Ion flow 5 is applied to the lt film 3 to perform ion implantation. The conditions for ion implantation are, for example, boron ions, acceleration voltage 5oKeV, dose amount 5x1o'', tz%4
It was executed with In addition, the conditions for ion implantation (implantation) (bow 1
, the ions were selected from voronophrine, alkone, and silicon, and the implantation amount was 3×1015 to 3×10.
It was possible to optimally set the acceleration voltage to 15 ions/Ca + sc) KeV or less.

+)ij述のイオン注入処理を施しだ後、通常の平行平
板型電極構造を有するイオンエツチング装置を使って、
エツチングガスとして四塩化炭素を用いて、リアクティ
ブイオンエツチングを行なう。このイオンエツチングに
よれば、先のイオン注入工程においてパターン開孔部に
露出しているJ膜はその表面部分がイオン衝撃を受けて
、エツチング速度の高いダメージ層に変質しており、一
方、ノ第1・レジスト膜4はイオン衝撃によって、エツ
チング速度が低い層に改質される結果、エツチングされ
るべきAl膜3とその耐性マスクであるフォトレジスト
膜4とのエツチング速度比、すなわち、選択性が従来の
それよシ2〜3倍向上する。
+) After performing the ion implantation process described in ij, using an ion etching device with a normal parallel plate electrode structure,
Reactive ion etching is performed using carbon tetrachloride as an etching gas. According to this ion etching, the surface portion of the J film exposed in the pattern opening in the previous ion implantation process was subjected to ion bombardment and transformed into a damaged layer with a high etching rate. The first resist film 4 is modified into a layer with a low etching rate by ion bombardment, and as a result, the etching rate ratio between the Al film 3 to be etched and the photoresist film 4 serving as its resistance mask, that is, the selectivity is improved by 2 to 3 times compared to the conventional method.

イオン注入されたA/膜の表面は、アルミニウム酸化層
のばらつきを超えて、深いダメージ層が形成されるだめ
に、イオンエツチングでのエツチング速度が増速され、
表面全体で一様なエツチングが始ま・す、All全全体
してのエツチング速度の均一性が改善される。したがっ
て、微細寸法パターンに対しても高精度かつ均一な加工
が可能になった。また、バッチ処理を行なった場合にも
、処理間のばらつきは顕著に減少され、均一性が大幅に
向上した。−例を示すと、通常のAl膜およびフォトレ
ジスト膜を用いて、ボロンを、加速電圧50KeV、 
 ドーズ量5 X 10”イオン/c4の条件下でイオ
ン注入して、2μm寸法のパターニングのものをバッチ
処理でイオンエツチングを行なったところ、ウェハ間で
の均一性は95係以上であり、実質上バッチ間の差は解
消された。
On the surface of the ion-implanted A/film, the etching rate in ion etching is increased to form a deep damage layer that exceeds the variations in the aluminum oxide layer.
Uniform etching begins across the entire surface, improving the uniformity of the etching rate over the entire surface. Therefore, it has become possible to process even fine-sized patterns with high precision and uniformity. Also, when batch processing was performed, the variation between treatments was significantly reduced and the uniformity was significantly improved. - To give an example, using an ordinary Al film and a photoresist film, boron is
When ion implantation was performed at a dose of 5 x 10" ions/c4 and ion etching was performed in a batch process on a pattern with a size of 2 μm, the uniformity among wafers was 95 coefficients or higher, and it was practically Differences between batches were eliminated.

発明の効果 本発明によれば、A7膜表面のアルミニウム酸化層の影
響を除去したイオンエツチングが可能になり、この結果
、人l膜を電極配線層とする電極加工が均一かつ高精度
に実現されるようになり、たとえば、微細パターンを必
要とする超高集積度半導体装置や高周波半導体装置など
の電極配線形成が一段と容易になるなど、本発明の効用
は太きいものである。
Effects of the Invention According to the present invention, it is possible to perform ion etching that removes the influence of the aluminum oxide layer on the surface of the A7 film, and as a result, electrode processing using the human film as an electrode wiring layer can be realized with uniformity and high precision. For example, the present invention has great benefits, such as making it easier to form electrode wiring for ultra-high-integration semiconductor devices and high-frequency semiconductor devices that require fine patterns.

4%+7−11111vノ1nl=1”’ヨti7L’
15第1図〜第4図は本発明の実施例を示す工程順断面
図である。
4%+7-11111vノ1nl=1"'Yoti7L'
15 FIGS. 1 to 4 are process-sequential sectional views showing an embodiment of the present invention.

1・・・・・半導体基板、2・・・・・・二酸化シリコ
ン、3−・・・・Al膜、4・・・・・・フォトレジス
ト膜、5・・・・・イオン流。
1...Semiconductor substrate, 2...Silicon dioxide, 3-...Al film, 4...Photoresist film, 5...Ion flow.

Claims (1)

【特許請求の範囲】 (1)アルミニウムを含む金属膜にイオン注入処理を施
した後、ドライエツチングを行なうことを特徴とする電
極配線形成方法。 ?)アルミニウムを含む金属膜がフォトレジストパター
ンでおおわれ、イオン注入処理が前記フォトレジスト面
とあわせて行なわれる特許請求の範囲第1項に記載の電
極配線形成方法。 (3)イオン注入処理が注入イオンがボロン、リン。 アルゴン、ンリコンのいずれかであり、その注入量が3
×10〜3×1015イオン/ Caで加速電圧が60
KeV以下の条件で行なわれる特許請求の範囲第1項も
しくは第2項に記載の電極配線形成方法。
[Scope of Claims] (1) A method for forming electrode wiring, characterized in that a metal film containing aluminum is subjected to ion implantation treatment, and then dry etching is performed. ? 2. The electrode wiring forming method according to claim 1, wherein a metal film containing aluminum is covered with a photoresist pattern, and ion implantation treatment is performed in conjunction with the photoresist surface. (3) In the ion implantation process, the implanted ions are boron and phosphorus. Either argon or argon, and the injection amount is 3
×10~3×1015 ions/Ca with acceleration voltage of 60
The electrode wiring forming method according to claim 1 or 2, which is carried out under conditions of KeV or lower.
JP21032082A 1982-11-30 1982-11-30 Formation of electrode wiring Pending JPS59100537A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21032082A JPS59100537A (en) 1982-11-30 1982-11-30 Formation of electrode wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21032082A JPS59100537A (en) 1982-11-30 1982-11-30 Formation of electrode wiring

Publications (1)

Publication Number Publication Date
JPS59100537A true JPS59100537A (en) 1984-06-09

Family

ID=16587470

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21032082A Pending JPS59100537A (en) 1982-11-30 1982-11-30 Formation of electrode wiring

Country Status (1)

Country Link
JP (1) JPS59100537A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009231424A (en) * 2008-03-21 2009-10-08 Dainippon Printing Co Ltd Method of manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009231424A (en) * 2008-03-21 2009-10-08 Dainippon Printing Co Ltd Method of manufacturing semiconductor device

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