JPS63181428A - Formation of resist pattern - Google Patents
Formation of resist patternInfo
- Publication number
- JPS63181428A JPS63181428A JP1470287A JP1470287A JPS63181428A JP S63181428 A JPS63181428 A JP S63181428A JP 1470287 A JP1470287 A JP 1470287A JP 1470287 A JP1470287 A JP 1470287A JP S63181428 A JPS63181428 A JP S63181428A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- thin film
- pattern
- electron beam
- assembly
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 239000010409 thin film Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 17
- 238000010894 electron beam technology Methods 0.000 claims abstract description 16
- 239000010408 film Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 229920001940 conductive polymer Polymers 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 abstract description 2
- 239000004372 Polyvinyl alcohol Substances 0.000 abstract description 2
- 238000001020 plasma etching Methods 0.000 abstract description 2
- 229920002451 polyvinyl alcohol Polymers 0.000 abstract description 2
- 229920000642 polymer Polymers 0.000 abstract 3
- 230000005611 electricity Effects 0.000 abstract 2
- 229920001296 polysiloxane Polymers 0.000 abstract 2
- 229910052799 carbon Inorganic materials 0.000 abstract 1
- 238000006073 displacement reaction Methods 0.000 abstract 1
- 239000002245 particle Substances 0.000 abstract 1
- 229920006254 polymer film Polymers 0.000 abstract 1
- -1 polyphenylsiloxane Polymers 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- MLFHJEHSLIIPHL-UHFFFAOYSA-N isoamyl acetate Chemical compound CC(C)CCOC(C)=O MLFHJEHSLIIPHL-UHFFFAOYSA-N 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical class [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 description 1
- 125000001495 ethyl group Chemical group [H]C([H])([H])C([H])([H])* 0.000 description 1
- 229940117955 isoamyl acetate Drugs 0.000 description 1
- 229920003986 novolac Polymers 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Electron Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は電子ビーム露光を用いたレジストパターンの形
成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of forming a resist pattern using electron beam exposure.
従来の技術
半導体装置のパターンが微細化されるにつれて電子ビー
ム露光がパターン形成に用いられるようになった。この
電子ビーム露光において、多層レジストを使用した場合
、下層のレジストの膜厚が厚いと、入射電子により下層
レジストが帯電し、電子ビームが曲げられて描画パター
ンの位置ずれが生じる。この問題を解決するために、レ
ジスト間に導電性を持つＳｉ薄膜を中間層として配置す
る対策が講じられている。しかしながら、Ｓｉ薄膜の形
成には、プラズマＣＶＤあるいは蒸着などの処理を採用
する必要がある。これらの工程は、塗布、熱処理工程な
どからなるホトレジスト工程とは異質なものであり、工
程が複雑化し、コストがかかる問題がある。さらに、２
層構造のレジストを用いる場合には、本来、不必要であ
る導電性層を追加しなければならない問題がある。2. Description of the Related Art As the patterns of semiconductor devices have become finer, electron beam exposure has come to be used for pattern formation. In this electron beam exposure, when a multilayer resist is used, if the lower resist layer is thick, the lower resist layer will be charged by the incident electrons, and the electron beam will be bent, causing a positional shift in the drawn pattern. In order to solve this problem, measures have been taken to arrange a conductive Si thin film as an intermediate layer between the resists. However, it is necessary to employ processes such as plasma CVD or vapor deposition to form the Si thin film. These steps are different from the photoresist step, which includes coating, heat treatment, etc., and have the problem of complicating the steps and increasing costs. Furthermore, 2
When using a layered resist, there is a problem in that an unnecessary conductive layer must be added.
発明が解決しようとする問題点
多層レジストを用いて電子ビーム露光を行った場合、入
射電子による帯電のために、電子ビームが曲げられ、こ
のため、描画パターンの位置ずれが生じるが、従来の方
法では、これの排除ができず、さらに、導電性薄膜を形
成する工程が複雑であるため、これに対応可能な装置価
格が高くなる問題もあった。Problems to be Solved by the Invention When electron beam exposure is performed using a multilayer resist, the electron beam is bent due to charging by incident electrons, resulting in misalignment of the drawn pattern, but conventional methods However, this problem cannot be eliminated, and furthermore, since the process of forming the conductive thin film is complicated, there is also the problem that the cost of equipment that can handle this process becomes high.
問題点を解決するための手段
本発明は、このような問題を解決するものであシ、基板
上に形成した２層以上の多層レジストの１層を導電性高
分子薄膜となし、この多層レジストに電子ビーム露光を
施してレジストパターンの形成を行う方法である。Means for Solving the Problems The present invention is intended to solve such problems.One layer of a multilayer resist of two or more layers formed on a substrate is a conductive polymer thin film, and this multilayer resist In this method, a resist pattern is formed by subjecting the resist pattern to electron beam exposure.
作用
本発明のパターン形成方法によれば、入射電子によるレ
ジストの帯電が防止される。Effect: According to the pattern forming method of the present invention, charging of the resist due to incident electrons is prevented.
実施例
以下に第１図〜第３図に基いて本発明の実施例について
説明する。先ず、シリコン基板１の表面上に導電性高分
子薄膜２として、例えば、カーボン微粉末を添加したポ
リビニルアルコールの薄膜を、約２μｍの厚さに塗布し
、次いで、２００℃。Embodiments Below, embodiments of the present invention will be described based on FIGS. 1 to 3. First, a thin film of polyvinyl alcohol to which fine carbon powder has been added, for example, is applied as a conductive polymer thin film 2 on the surface of a silicon substrate 1 to a thickness of about 2 μm, and then heated at 200°C.
３０分の熱処理を施したのち、シリコン系レジスト３と
して例えば、クロロメチル化ポリシセニールシロキサン
を塗布し、さらに１３０’Ｃ，３０分の熱処理を施すこ
とによって２層構造のレジストを形成する（第１図）。After heat treatment for 30 minutes, a chloromethylated polyscenyl siloxane, for example, is applied as the silicon-based resist 3, and heat treatment is further performed at 130'C for 30 minutes to form a two-layer resist. Figure 1).
この後、露光量３０μＣ／ｄで電子ビーム露光し、酢酸
イソアミル：エチルセルソルブニ１：３の現像液を舟い
て１分間現像し、シリコン系レジストパターン４を形成
する（第２図）。最後に、０２ガスを用いた反応性イオ
ンエツチングにより、導電性高分子膜２をエツチングし
て導電性高分子薄膜パターン６を形成する（第１図）。Thereafter, electron beam exposure was performed at an exposure dose of 30 μC/d, and a developing solution of isoamyl acetate:ethyl cellulone 1:3 was added and developed for 1 minute to form a silicon-based resist pattern 4 (FIG. 2). Finally, the conductive polymer film 2 is etched by reactive ion etching using O2 gas to form a conductive polymer thin film pattern 6 (FIG. 1).
以上の過程を経て形成されたレジストパターンでは、±
０．１μｍ（３σ）の高い重ね合せ精度がえられた。な
お、導電性高分子薄膜２０部分を通常のホトレジスト、
例えばノボラック系ポジ形ホトレジスト膜とした場合、
形成されたレジストパターンの重ね合せ精度は帯電によ
る位置ずれのため、±０．７μｍ（ｓσ）の低い精度で
あった。The resist pattern formed through the above process has ±
A high overlay accuracy of 0.1 μm (3σ) was obtained. Note that the conductive polymer thin film 20 portion is made of ordinary photoresist,
For example, when using a novolak-based positive photoresist film,
The overlay accuracy of the formed resist patterns was as low as ±0.7 μm (sσ) due to positional deviation due to charging.
なお、以上説明した実施例では、上層がシリコン系レジ
スト層、下層が導電性高分子薄膜の２層レジスト構造で
あったが、この例に限られるものではなく、例えば、下
層を導電性高分子薄膜、中間層を塗布酸化膜とし、さら
に、上層を電子ビームレジスト層とした３層レジスト構
造とするなどの多層レジスト構造としてもよい。In the embodiments described above, the upper layer is a silicon-based resist layer and the lower layer is a conductive polymer thin film, but the resist structure is not limited to this example. For example, the lower layer is a conductive polymer thin film. A multilayer resist structure may be used, such as a three-layer resist structure in which a thin film or an intermediate layer is a coated oxide film, and an upper layer is an electron beam resist layer.
発明の効果
以上の説明から明らかなように、本発明のレジストパタ
ーンの形成方法によれば、入射電子による帯電を排除し
た電子ビーム露光が可能となり、このため、電子ビーム
が曲げられることはなく、パターン歪みおよびパターン
の位置ずれのないノ（ターンを形成することができる。Effects of the Invention As is clear from the above explanation, according to the resist pattern forming method of the present invention, electron beam exposure can be performed without charging due to incident electrons, and therefore the electron beam is not bent. Turns can be formed without pattern distortion or pattern misalignment.
また、導電性高分子薄膜の形成も簡単な処理で可能であ
るため、工程が複雑となることはなく、さらに、複雑な
工程に対応可能な装置を使用する必要もないため装置価
格の低減をはかることができる。In addition, since the formation of a conductive polymer thin film is possible through simple processing, the process does not become complicated.Furthermore, there is no need to use equipment that can handle complicated processes, reducing equipment costs. It can be measured.
第１図〜第３図は本発明の方法によシバターン形成がな
される過程を示す図である。
１・・・・・・シリコン基板、２・・・・・・導電性高
分子薄膜、３・・・・・・シリコン系レジスト、４・・
・・・・シリコン系レジストパターン、５・・・・・・
導電性高分子薄膜パターン０
代理人の氏名 弁理士 中 尾 敏 男 ほか１名Ｊ−
シリ］ン丞しジ゛スト
第 １１！１FIGS. 1 to 3 are diagrams showing the process of forming a shiver pattern by the method of the present invention. 1... Silicon substrate, 2... Conductive polymer thin film, 3... Silicon resist, 4...
...Silicon-based resist pattern, 5...
Conductive polymer thin film pattern 0 Name of agent Patent attorney Toshio Nakao and 1 other person J-
Series 11!1
Claims (1)
高分子薄膜となし、この多層構造レジスト膜に電子ビー
ム露光処理を施すことを特徴とするレジストパターンの
形成方法。1. A method for forming a resist pattern, which comprises forming one layer of a multilayer resist film formed on a substrate as a conductive polymer thin film, and subjecting the multilayer resist film to an electron beam exposure process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1470287A JPS63181428A (en) | 1987-01-23 | 1987-01-23 | Formation of resist pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1470287A JPS63181428A (en) | 1987-01-23 | 1987-01-23 | Formation of resist pattern |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63181428A true JPS63181428A (en) | 1988-07-26 |
Family
ID=11868511
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1470287A Pending JPS63181428A (en) | 1987-01-23 | 1987-01-23 | Formation of resist pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63181428A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63254728A (en) * | 1987-04-10 | 1988-10-21 | Matsushita Electronics Corp | Forming method for resist pattern |
| US5019485A (en) * | 1988-10-13 | 1991-05-28 | Fujitsu Limited | Process of using an electrically conductive layer-providing composition for formation of resist patterns |
| US5783363A (en) * | 1992-05-28 | 1998-07-21 | National Semiconductor Corporation | Method of performing charged-particle lithography |
| WO2004025369A3 (en) * | 2002-09-04 | 2004-07-15 | Infineon Technologies Ag | Method for lithographically structuring a substrate, and lacquer system |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62272528A (en) * | 1986-05-20 | 1987-11-26 | Fujitsu Ltd | Forming method for pattern |
-
1987
- 1987-01-23 JP JP1470287A patent/JPS63181428A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62272528A (en) * | 1986-05-20 | 1987-11-26 | Fujitsu Ltd | Forming method for pattern |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63254728A (en) * | 1987-04-10 | 1988-10-21 | Matsushita Electronics Corp | Forming method for resist pattern |
| US5019485A (en) * | 1988-10-13 | 1991-05-28 | Fujitsu Limited | Process of using an electrically conductive layer-providing composition for formation of resist patterns |
| US5783363A (en) * | 1992-05-28 | 1998-07-21 | National Semiconductor Corporation | Method of performing charged-particle lithography |
| WO2004025369A3 (en) * | 2002-09-04 | 2004-07-15 | Infineon Technologies Ag | Method for lithographically structuring a substrate, and lacquer system |
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