JPS5897755A - Information processor - Google Patents

Abstract

PURPOSE:To increase the transfer speed of data between an external and internal memories and to increases a processing speed, by designating the address of a memory by means of the 1st and 2nd address designating means with respective different timings. CONSTITUTION:The 2nd address counter 20 that can designate the address of an internal memory 13 is provided in addition to the 1st address counter 15 which can designate the address of the memory 13. The counter control signal 21 which indicates the working of the counter 20 is supplied from a memory control circuit 22 which is provided outside a single chip microcomputer 12. The circuit 22 also controls an external memory 23. Then the counters 15 and 20 give the accesses to the memory 13 with respective different timings. As a result, a double transfer of data is possible between the memories 23 and 13. This simplifies the transfer of data with a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device having a CPU function that decodes instructions and processes programs based on the results, and in particular, enables data transfer between an external memory and an external device. It concerns information processing equipment.

The above-mentioned device has the ability to perform data processing using the memory contained within the device. This memory consists of a program memory (ROM) containing the program (instructions) and a data memory (RAM) containing the data, and is generally integrated on a single chip; Represented.

Conventionally, Yuzu's single-chip microcomputer had the following configuration. That is, as shown in FIG. 1, a single-chip microcomviator 1 has an internal memory 2 in which programs and data are stored. Addressing of the internal memory 2 is performed by an IP quadrature counter 3 which specifies the address of the instruction memory section and an address counter 4 which specifies the address of the data memory section. However, since this microcomputer 1 is integrated on a single chip, the capacity of the internal memory 2 is fixed, and the memory capacity can be expanded by I-j.
The drawback was that it was thin. On the other hand, like the single-chip microphone converter 5 shown in FIG. Some have been improved to allow you to expand your memory even when you run out of space. Addressing of the external memory 6 and the internal memory 7 is carried out by a program counter 8 and an address counter 9 within the single-chip microcombinator as in the case of FIG. 1 above.

However, when accessing the external memory 6, a timing control mechanism consisting of a control circuit 10X for address signals and a control circuit 11 for data is involved, and because it is located outside the chip, the load is heavy. As a result, the memory access time is disadvantageous in that it takes a long time to access the internal memory 7.

In addition, you can specify internal memory addresses to read and write data for use inside the device, write data from outside the device to internal memory, and output other data to the outside. The same counter (or register may be used) is required to specify the internal memory address for this purpose, and the procedure control for this is complicated and takes a long time. %, since the addressing counter is designed to be controlled based on instructions read from the internal memory, data transfers between external memory and internal memory may not be duplicated within an instruction execution period. I couldn't get it to run. That is, data transfer between the external memory and the internal memory requires a separate dedicated data transfer command execution period.

SUMMARY OF THE INVENTION An object of the present invention is to provide an information island device that can transfer data between an external memory and an internal memory at high speed and execute programs without reducing processing speed.

The present invention has a memory capable of reading and writing information, and first and second addressing means for specifying addresses of the memory, and the first and second addressing means are arranged at different timings. The memory is characterized in that it is adapted to address the memory.

According to the present invention, since a plurality of independent memory addressing means are provided, a large number of memory accesses can be made within an instruction execution period, and accordingly high-speed processing can be achieved. Further, since the address content change procedure processing required of each address specifying means is relaxed, the control thereof becomes extremely simple.

Next, one embodiment of the present invention will be described using the drawings.

FIG. 3 is a block diagram thereof. The single-chip microcombinator 12 has an internal memory 13, a program counter 14, and a first address counter 15, the operation and function of which may be the same as the prior art shown in FIGS. . That is, a program counter 14 for specifying program memory (ROM) and data memory (RAM).
W for designation, 1 count operation of address counter 15 (
The operations (increasing or decreasing the contents of the counter) are determined by the execution of instructions in the ROM. Specifically, by executing processing based on the instructions stored in the internal memory 13, that is, the instruction addressed by the program counter 14 is read into the instruction register 16, and the instruction is sent to the instruction decoder. 17 outputs count control signals 18 and 19 that instruct the counter operations of program counter 14 and $1 address counter 15.

In this embodiment, in addition to specifying the address of the internal memory 13 using this first address counter, the internal memory 13 is also specified by the first address counter.
A #J2 address counter 20 is provided which can specify an address. A count control signal 21 that instructs the counting operation of the silver 2 address counter 20 is sent to a memory control 1 circuit 22 external to the single-chip microcombinator 12.
Well supplied. At the same time, the memory control circuit 1622 also controls the external memory 23. Program counter 14, first address counter 15 and second address counter 2
1 cannot access the internal memory 13 at the same time. As shown in Figure 5, the execution time of one instruction is time-divided for use.

That is, the execution time of one instruction is, for example, I/iT+, Tt, Tl,
If there are four timings T4, the program counter 14 has TI shown by waveform 24, the first address counter 15 has T shown by waveform 25, and the second address counter 20 has waveform 26. memory 1
3 to be accessed. As a result, one using the program counter 14 and the first address counter 15
During the execution period of one instruction, the external memory 23 and 182 address counter 2 specified by the memory control circuit 22
Data transfer can be performed once and again with the internal memory 13 addressed by 0.

As is clear from the above, data transfer between the internal memory 13 and the external memory 23 can be performed quickly and easily, so that the memory capacity can be expanded externally. Furthermore, since the program is always executed only on the internal memory 13, there is no reduction in execution speed due to accessing the external memory. Furthermore, although the m2 address counter may be controlled using only internal control signals, if it is controlled using two, an external control signal and an internal clock signal, as in the embodiment, it is possible to control the m2 address counter using only an internal control signal. There is no synchronization error.

However, the present invention is not limited to single-chip microcombinators, but is also useful in conventional microprocessors and multiprocessor systems.

[Brief explanation of drawings]

1 and 2 are a block diagram of a main part of a conventional single-chip microconviator, a block diagram of a main part of a single-chip microcombinator showing an embodiment of the present invention, and FIG. FIG. 4 is a timing chart showing the operation timing in the embodiment shown in the third section. 1...Single chip microcomputer, 2.
...Internal memory, 3...Program counter, 4...Address counter, 5...
・Single tick micro combinator, 6...external memory, 7...internal memory, 8...
Program 2m counter, 9...Address counter, 10...111JI41 circuit, 11...
...Control III circuit, 12...Single chip microcomputer, 13...Internal memory, 14
...Program counter, 15...
$1!1 Address counter, 16...Instruction register, 17...Instruction decoder, 1B...
- Counter control signal line, 19... Counter control signal line, 20... tII42 address counter, 21... Counter control signal line, 22...
...Memory control circuit, 23...External memory, 2
4125.26... Waveform.

Claims (1)

[Claims] It has a memory from which information can be read and written, and first and second addressing means for specifying an address of the memory, and the first and second addressing means address the memory at different timings. An information processing device whose characteristic is that the address is fixed.