JPH0310977B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to data processing devices, and more particularly to improvements related to memory access in data processing devices.

[Background of the invention]

In general, in conventional data processing devices, one memory access circuit accesses the storage device to read instructions, read data, or write data, so the instruction execution time is calculated by multiplying the storage device access time by the number of accesses. Determined by internal processing time. Therefore, efforts are being made to speed up the processing by speeding up internal processing through multi-stage advance control and by shortening memory access time by introducing cache memory. However, even higher speeds are desired. A detailed description of such a data processing device can be found, for example, in Chapter 3 of ``System Design of Electronic Computers'' by Koji Hajima, published by Sanpo Co., Ltd.

[Purpose of the invention]

An object of the present invention is to provide a means for realizing further speeding up of a data processing device.

[Summary of the invention]

In order to further speed up processing, the data processing device according to the present invention enables storage devices in the same memory space to be physically separated from the perspective of a program.
The main point is that each is provided with an independent memory access circuit.

By the way, depending on the separation of the storage device, separation loss of the storage device may occur. Therefore, in the present invention, processing capacity is increased by providing means for identifying separation and integration of storage devices, means for interconnecting memory access circuits, and means for resolving conflicts among memory access circuits. If not so much is needed, an economical system can be achieved by integrating storage devices.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic block diagram showing one embodiment of the present invention. In this figure, 1 is a processing unit (CPU), including a sequence control unit (SEQ) 1-1, an arithmetic unit (ALU) 1-2, and a control unit (CTL) 1-
Consists of 3. 2 and 3 are physically separate storage devices (MM) in the same memory space (from the perspective of the program). In this embodiment, as shown in FIG. 2, program instructions are stored in one memory device (MM) 2, and data are stored in the other memory device (MM) 3. Processing device 1 reads an instruction from storage device 2 and stores the data (in storage device 3) specified by the operand address of the instruction.
, executes the operation indicated by the instruction code of the instruction.

Referring again to FIG. 1, the order control unit 1-1 includes a program counter that specifies the execution address of a program, an update circuit for the program counter, a memory access circuit 4 that reads instructions from the address of the storage device 2 specified by the program counter, and the like. . Arithmetic unit 1-2
is a part that executes instructions read from the storage device 2, and includes an accumulator, an arithmetic unit, and a storage device 3.
It consists of a memory access circuit 5 for reading and writing data. The control unit 1-3 includes a circuit that generates various timings in the processing device 1, an instruction decoder that decodes instructions read from the storage device 2, a control circuit for the order control unit 1-1 and the calculation unit 1-2, etc. and controls the entire processing device 1.

FIG. 3 shows the instruction execution timing of the processing device 1. If you explain while referring to this diagram,
The execution of the instruction is the cycle S _o with the minimum timing,
_The cycle time is the internal processing time of the processing device ₁ . As the storage devices 2 and 3, storage devices whose access time is shorter than the cycle time are selected. In each cycle, the order controller 1-1 uses the address n,
Instructions n+1, n+2, ... are sequentially read from the storage device 2 (instruction read), the arithmetic unit 1-2 performs internal processing of these instructions, and the memory access circuit 5 reads or writes data to the storage device 3. (data read/write). As is clear from FIG. 3, well-known pipeline control is used from instruction reading to internal processing, while program data reading/writing is executed in the same cycle as internal processing. Therefore, an instruction can be executed substantially in one cycle, and processing speed can be greatly improved.

Now, as mentioned above, high-speed processing is possible when the storage device is physically divided, but the device tends to be more expensive than when there is only one storage device, and there is a risk of loss due to partitioning of the storage device. be. Therefore, if high speed is not required, a configuration is desired in which data processing can be performed by integrating storage devices into one device.
This embodiment has such a configuration. This will be explained with reference to FIG.

FIG. 4 is a schematic block diagram of the storage device and related parts inside the processing device 1. As shown in FIG. In this figure, reference numeral 6 denotes a competition circuit for sorting out competition between memory access requests from memory access circuits 4 and 5. The input terminal 7 of this competition circuit 6 is given a "1" level when the storage devices are separated as shown in FIG. ) is given a “0” level. The order control unit 1-1 is provided with a three-state driver 8 for addresses and a buffer 9 for read data. Similarly, the arithmetic unit 1-2 is provided with a three-state driver 11 for addresses, a driver 12 for write data, and a buffer 13 for read data. The address drivers 8 and 11 are of a three-state type so that they can be interconnected when integrating storage devices as will be described later.

Next, the operation when storage devices are integrated will be explained. In this case, as shown in the figure, the order control unit 1-1
The address output terminal 15 of and the address output terminal 16 of the calculation section 1-2, and the read data input terminal 17 of the order control section 1-1 and the read data input terminal 18 of the calculation section 1-2 are connected by wires L1 and L2, respectively. It is commonly connected to the address input terminal and data output terminal of the integrated storage device 30. The write data output terminal 19 is connected to a data input terminal of the integrated storage device 30. Furthermore, a “0” level is applied to the terminal 7.

The memory access circuits 4 and 5 send signals 4-1 and 5- to the contention circuit 6 when a memory access request occurs.
1 respectively. For example, one signal 4-1
(or 5-1) is turned on. In this case, the contention circuit 6 transmits the signal 4-2 (or 5-2) to the memory access circuit 4 (or 5) for which the request is occurring at the time when the integrated storage device 30 becomes accessible. Turn on and allow the memory access request. Permitted memory access circuit 4 (or 5) receives signal 4-3 (or 5).
-3), activates the address buffer 8 (or 11), and transfers the address to the unified storage device 30.
Send to. When the memory access request is a data read request, read data from the integrated storage device 30 is read into the order control unit 1-1 (or the calculation unit 1-2) through the buffer 9 (or 13). If the request from the memory access circuit 5 is granted and the request is a data write request, the driver 1
The write data is applied to the integrated storage device 30 via 2 and written therein.

When memory access requests occur simultaneously in the memory access circuits 4 and 5 and the signals 4-1 and 5-1 are turned on at the same time, the conflict circuit 6 sorts out the conflicts between the two requests and requests one of the memory access circuits 4 or 5. The request is permitted by turning on the signal 4-2 or 5-2 only for the request.

When the storage devices are integrated in this way, the memory access circuits 4 and 5 cannot perform memory access at the same time. Therefore, the instruction execution timing is as shown in FIG. 5, and the instruction execution time is 2 cycle time.

When separating the storage devices as shown in Figure 1,
The address output terminal 15 and read data input terminal 17 of the order control section 1-1 are connected to one of the storage devices 2, and the address output terminal 16, write data output terminal 19 and read data input terminal 18 of the calculation section 1-2 are connected to one of the storage devices 2. It is connected to the other storage device 3, and a "1" level is applied to the input terminal of the competition circuit 6.
In this case, the competition circuit 6 always turns on the signals 4-2 and 5-2. Therefore, each memory access circuit 4, 5 is in a state where memory access is always permitted, and therefore, each memory access circuit 4, 5 independently accesses the memory device 2, 5.
3 can be accessed at any time.

As described above, in this embodiment, processing speed can be achieved by separating the storage devices, and if high speed is not required, the storage devices can be integrated to configure an economical system. .

Note that the order control unit 1-1 side may also be configured to be able to write data. In this case, if the write data driver is of a three-state type and the outputs of the driver can be integrated when the storage devices are integrated, the storage devices can be separated and integrated as described above.

〔Effect of the invention〕

As explained above, according to the present invention, for example, instruction read and program data access can be executed in parallel to a separate storage device, so that instruction execution time can be shortened, and faster data processing can be achieved. It becomes possible to realize the device. Furthermore, if the processing power of the data processing device is not so required, an economical system can be realized by integrating storage devices.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram showing one embodiment of the present invention, FIG. 2 is an explanatory diagram of separation of storage devices, FIG. 3 is a timing diagram showing instruction execution timing when storage devices are separated, and FIG. 4 5 is a block diagram showing the configuration of main parts inside the processing device, and FIG. 5 is a timing chart showing instruction execution timing when storage devices are integrated. 1...Processing unit (CPU), 1-1...Sequence control unit (SEQ), 1-2...Arithmetic unit (ALU), 1-3
... Control unit (CTL), 2, 3 ... Separated storage device, 4, 5 ... Memory access circuit, 6 ... Competition circuit, 8, 11 ... Three-state driver for address, 9, 13 ... ...Read data buffer, 12...Write data driver, 30...
...integrated memory.

Claims (1)

[Scope of Claims] 1. A data processing device that enables storage devices in the same memory space to be separated from each other when viewed from a program, and is provided with an independent memory access circuit for each, the data processing device being capable of identifying separation and integration of the storage devices. A data processing device comprising a first means, a second means for interconnecting the memory access circuits, and a third means for sorting out conflicts between the memory access circuits. .