JPS5893090A - Matrix type liquid crystal display - Google Patents

Matrix type liquid crystal display

Info

Publication number
JPS5893090A
JPS5893090A JP56193526A JP19352681A JPS5893090A JP S5893090 A JPS5893090 A JP S5893090A JP 56193526 A JP56193526 A JP 56193526A JP 19352681 A JP19352681 A JP 19352681A JP S5893090 A JPS5893090 A JP S5893090A
Authority
JP
Japan
Prior art keywords
liquid crystal
tft array
storage capacitor
gate
crystal display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56193526A
Other languages
Japanese (ja)
Inventor
隆夫 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56193526A priority Critical patent/JPS5893090A/en
Publication of JPS5893090A publication Critical patent/JPS5893090A/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 この発明は複数個のゲート線、及びソース線を備えた複
数個のTPT等の能動素子の他、蓄積コンデンサー等を
有するTFTアレイ等の半導体装置のゲート電極、ゲー
ト絶縁膜、蓄積コンデンサー電極、及びMvt体の構成
材料、及びその製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to gate electrodes and gate insulators of semiconductor devices such as TFT arrays having storage capacitors, etc., as well as active elements such as TPTs having a plurality of gate lines and source lines. The present invention relates to constituent materials of membranes, storage capacitor electrodes, and Mvt bodies, and methods of manufacturing the same.

第1図はTFTアレイの構成を、@2図はマトリクス型
液晶表示装置の構成を説明するための断面構造図である
。図において、(1)はゲート縁、(2)はソース線、
(3)はドレイン電極、(4月よTFT、(5)は表示
電極、(6)は蓄積コンデンサー、(7)は液晶、(8
)はTFTアレイ、(9)はTFTアレイ基板、 QO
は透明導電i、aaはカラーフィルター、(財)は対向
基板、(至)はマトリクス型液晶表示装置を示している
FIG. 1 is a cross-sectional structural diagram for explaining the configuration of a TFT array, and FIG. 2 is a cross-sectional structural diagram for explaining the configuration of a matrix type liquid crystal display device. In the figure, (1) is the gate edge, (2) is the source line,
(3) is the drain electrode, (April TFT), (5) is the display electrode, (6) is the storage capacitor, (7) is the liquid crystal, (8
) is TFT array, (9) is TFT array substrate, QO
denotes a transparent conductive i, aa a color filter, (goods) a counter substrate, and (to) a matrix type liquid crystal display device.

従来この種の装置として繭8図、第4図に示すものがあ
った。・第8図はTPTアレイ画素の平面図。
Conventionally, there have been devices of this type as shown in Fig. 8 and Fig. 4.・Figure 8 is a plan view of a TPT array pixel.

銅4図は第8図mV−W線における断面積構造図を示し
たものである。
Figure 4 shows a cross-sectional structural diagram taken along the line mV-W in Figure 8.

図において、(1)はゲート線、(2)はソース線、(
3)はドレイン電極、(5目よ表示電極、(8)はTF
Tアレイ。
In the figure, (1) is a gate line, (2) is a source line, (
3) is the drain electrode, (5th is the display electrode, (8) is the TF
T array.

゛(9)はTFTアレイ基板、a4は半導体、(2)は
蓄積コンデンサー電極、αQはゲート絶縁膜、Oは誘電
体を示している。
(9) is a TFT array substrate, a4 is a semiconductor, (2) is a storage capacitor electrode, αQ is a gate insulating film, and O is a dielectric.

まず、第1図、第2図とともにマトリクス型液晶表示装
−の構成を説明する。マトリクス型液晶表示装!1輪は
複数個のゲート線(υ、及びこnらのゲート線と証文す
るソース線(2)とを備え、その交点に例えばTPT 
(4)等の能動素子が形成さn、そのドレイン電極(3
)1表示電極(6)、及び信号蓄積コンデンサー(6)
を有する構造のTFTアレイ(8)を形成したTFTア
レイ基板(9)と、これと対向する透明導電1iQI、
赤、縁、青等のカラーフィルター(ロ)、を有する対向
基板斡及びこの側基板(9)、(ロ)の間に液晶(7)
が挾持された構造となっている。
First, the structure of a matrix type liquid crystal display device will be explained with reference to FIGS. 1 and 2. Matrix type liquid crystal display! One wheel is equipped with a plurality of gate lines (υ) and a source line (2) that certifies these gate lines, and a TPT wire is connected at the intersection thereof.
Active elements such as (4) are formed, and its drain electrode (3
) 1 display electrode (6), and signal storage capacitor (6)
A TFT array substrate (9) on which a TFT array (8) having a structure is formed, and a transparent conductive 1iQI substrate facing this,
A liquid crystal (7) between the opposing substrate (9), which has color filters (b) such as red, edge, and blue, and this side substrate (9), (b).
It has a sandwiched structure.

ひき続き、従来のTFTアレイ(8)を第8図、第4図
により説明する。TFTアレイ(8)はガラス等の絶縁
基板よりなるTFTアレイ基板(9)の表面に、ゲート
線a)となるAI等を例えば蒸着法等で形成し、その上
部にゲート絶縁膜(至)となる810.等を例えばスパ
ッター法等で形成、更にソースIIM(2)、)’レイ
ン電極(3)となるA1等を例えば蒸着法等で形成した
後に半導体(ロ)となる例えばアモルファスシリコン等
を、プラズマCVD法等で形成してTFT (4)を設
置する。この後蓄積コンデンサー(6)を例えば蓄積コ
ンデンサー電極に)となるIII!03等を蒸着法等で
形成した後、誘電体αηとして例えばStO,等をスパ
ッター法等で形成し1表示電極(5)、及び蓄積コンデ
ンサーの上部電極を兼ねる例えばIn2O2を例えば蒸
着法等で形成し、その一端を先に形成しt、ニドレイン
電極(3)に接続してTFTアレイ(8)が完成する。
Next, the conventional TFT array (8) will be explained with reference to FIGS. 8 and 4. The TFT array (8) is made of an insulating substrate such as glass, on the surface of which is formed an AI or the like that will become the gate line a), for example, by vapor deposition, and a gate insulating film (to) is formed on top of it. 810. For example, after forming A1, etc., which will become the source IIM (2), )' and rain electrode (3), by a vapor deposition method, etc., for example, amorphous silicon, etc., which will become the semiconductor (b), is formed by plasma CVD. The TFT (4) is then formed by a method or the like. After this, the storage capacitor (6) becomes, for example, a storage capacitor electrode) III! 03 etc. by a vapor deposition method, etc., a dielectric material αη, such as StO, is formed by a sputtering method, etc., and then, for example, In2O2, which also serves as the 1 display electrode (5) and the upper electrode of the storage capacitor, is formed by a vapor deposition method, etc. Then, one end of the TFT array (8) is formed first and connected to the NiDrain electrode (3), thereby completing the TFT array (8).

ところでマトリクス型液晶表示にもちいるTFTアレイ
に要求される特性は、  TPTのOFF時のドレイン
電流、  (105(OFF) )とON時の一流(X
DS(ON))との比重Di(ON)/ID5(OFF
)  が108以上必要であり、又TFTの感度、利得
を示す相互コンダクタンス(pm)が大きいことが必要
である。ここで、約600℃以下の低温プロセスで形成
可能な半4体、 例えばアモルファス、シリコンをもち
いたTPT等ではこの半導体とゲート絶縁膜との界面近
傍における。半導体中のキャリヤーの電界効果移動度(
ロ)が、この半導体に例えば単結晶シリコン等を使用し
た場合に比し、極めて小さく(例えば0、ii cm”
/ V−s e を以下)液晶号駆動するに必要な電圧
(電流)を得ることが困難であり、極めて大型(’l’
−)1i1/ゲート長比の大きな)、かつ大面積のTP
Tの形成が必要となり1例えば第8図に示しり大型のT
PTと小さd表示電極の構成となる・一方マトリクス型
液晶表示等の画像表示では。
By the way, the characteristics required of a TFT array used in a matrix type liquid crystal display are the drain current (105 (OFF)) when the TPT is OFF and the current (X) when the TPT is ON.
DS(ON)) and specific gravity Di(ON)/ID5(OFF
) is required to be 108 or more, and it is also necessary that the transconductance (pm), which indicates the sensitivity and gain of the TFT, be large. Here, in the case of a half body that can be formed by a low-temperature process of about 600° C. or lower, such as an amorphous TPT using silicon, it is located near the interface between the semiconductor and the gate insulating film. Field effect mobility of carriers in semiconductors (
b) is extremely small (e.g. 0.ii cm"
/ V-s e below) It is difficult to obtain the voltage (current) necessary to drive the liquid crystal, and it is extremely large ('l'
-) Large 1i1/gate length ratio) and large area TP
For example, as shown in Fig. 8, it is necessary to form a large T.
On the other hand, image displays such as matrix type liquid crystal displays have a structure of PT and small d display electrodes.

その解像度の制約から単位画素の最大寸法は、約800
 iクロンメートル0以下程度に小さくする必要がある
Due to resolution constraints, the maximum size of a unit pixel is approximately 800
It is necessary to make it as small as 0 or less ichronmeter.

以上に説明したように、従来例ではマトリクス型液晶表
示において、通常表示上欠陥となるTPTの設置面積が
大きくなり1表示電極の設置面積が減少する結果1表示
性能の目安となる単位画素面積に占める表示電極面積の
比、すなわち開口率(以下開口率と称する)が低下する
と共に比較的大容量を必要とする信号蓄積コンデンサー
の形成可能面積等が低下し、良好な表示性能を有するマ
トリクス型液晶表示装置が得ら口ないといった欠点があ
った。
As explained above, in conventional matrix-type liquid crystal displays, the installation area of TPT, which usually causes display defects, increases and the installation area of one display electrode decreases, resulting in a reduction in unit pixel area, which is a measure of one display performance. A matrix-type liquid crystal that has good display performance because the ratio of the display electrode area, that is, the aperture ratio (hereinafter referred to as aperture ratio), is reduced, and the area where a signal storage capacitor, which requires a relatively large capacity, can be formed is reduced. The disadvantage was that the display device was not very attractive.

この発明は前述のような従来のものの欠点を除去するた
めになされたもので、ヤトリクス型液晶表示装置等にも
ちいるTFTアレイにおいて、ゲート電極、及び蓄積コ
ンデンサー電極の構成材料にTiをもちい、この表面を
陽極酸化して、ゲート絶縁膜及び蓄積コンデンサーの誘
電体とすることを特徴としている。
This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and it uses Ti as the constituent material of the gate electrode and storage capacitor electrode in a TFT array used in a YATRIX type liquid crystal display device, etc. The feature is that the surface is anodized to serve as the gate insulating film and the dielectric of the storage capacitor.

以下この発明の一笑施例を第6図、第6図により説明す
る。第6図はこの発明のTFTアレイ画素の部分平面図
、第61は第6図■−■線における断面構造図を示して
いる。図において、(1)はゲート線、(2)はソース
線、(3)はドレイン電極、(5)は表示電極、(8)
はTFTアレイ%(9)はTFTアレイ基板、 C14
は半導体、 c1!1は蓄積コンデンサー%(m、(I
ll)l!ゲート絶縁膜、 (17)は誘電体を示して
いる。ひき続きその構成を説明する。
Hereinafter, a simple embodiment of this invention will be explained with reference to FIGS. FIG. 6 is a partial plan view of the TFT array pixel of the present invention, and FIG. 61 is a cross-sectional structural diagram taken along line 1--2 in FIG. In the figure, (1) is the gate line, (2) is the source line, (3) is the drain electrode, (5) is the display electrode, and (8) is the drain electrode.
is TFT array% (9) is TFT array substrate, C14
is the semiconductor, c1!1 is the storage capacitor% (m, (I
ll)l! The gate insulating film (17) shows the dielectric material. Next, I will explain its structure.

TFTアレイ(8)はガラス等の透明絶縁基板よりなる
TFTアレイ基板(9〕の表面に、まずゲート線(1)
及び蓄積コンデンサー電極に)となるTiを例えば蒸着
法等で形成し、ゲート線(1)及び蓄積コンデンサー電
極に)を陽極に例えば、溶質(硼酸アンモンン。
The TFT array (8) first has a gate line (1) on the surface of a TFT array substrate (9) made of a transparent insulating substrate such as glass.
Ti, which will become the gate line (1) and the storage capacitor electrode), is formed by, for example, vapor deposition, and the solute (ammonium borate) is formed on the gate line (1) and the storage capacitor electrode) as the anode.

溶媒(メタノール)等の非水化成液で一極酸化し。Unipolar oxidation is performed using a non-aqueous chemical solution such as a solvent (methanol).

ゲート絶縁膜−,及び′に積コンデンサーの誘電体動を
杉或した後1表示wt極(5)と蓄積コンテンサーの上
部電極を兼ねる1例えば1m103等の透明尋電膜を蒸
着法等で形成し1次いでソース縁(2)、及びドレイン
電極(3)となる例えばAg等を蒸M’h等で形成し先
に形成した表示電極(5)の一端に接続する。
After removing the dielectric material of the product capacitor on the gate insulating films and ', a transparent dielectric film of 1 m 103, etc., which also serves as the display wt electrode (5) and the upper electrode of the storage capacitor, is formed by vapor deposition or the like. First, a source edge (2) and a drain electrode (3), such as Ag, are formed using vaporized M'h or the like and connected to one end of the previously formed display electrode (5).

この後アモルファスシリコン等の半専体(ロ)を例えば
プラズマCVD 2等で形成、設【してTFTアレイ(
8)が完成する。
After this, a semi-dedicated material (b) of amorphous silicon, etc. is formed by, for example, plasma CVD 2, etc., and then a TFT array (
8) is completed.

この発明によるTFTアレイは以上のようにゲート絶縁
膜及び蓄積コンデンサーの誘電体が、それぞロゲート電
極及び蓄積コンデンサー電極を構成するTIを陽極酸化
法でその表面を酸化し、TiO2よりなる絶縁被膜を形
成した。安定な酸化膜TIO,は誘電率が大きく、ブル
ーカイトで約80.アナターゼで約80.ルチールで約
100等メ綽を有し、従来法の例でもちいたSSO,(
誘電率は約□(・8〜4)等に比較して極めて大きい。
As described above, in the TFT array according to the present invention, the dielectric material of the gate insulating film and the storage capacitor is formed by oxidizing the surface of the TI, which constitutes the rogate electrode and the storage capacitor electrode, respectively, by anodizing, and forming an insulating film made of TiO2. Formed. The stable oxide film TIO has a large dielectric constant, about 80. Approximately 80. SSO, which is made of rutile and has approximately 100 mag.
The dielectric constant is extremely large compared to about □ (·8 to 4).

このことはTFTの性能指数(μ°ε/l−”/L )
 (ここでμはキャリヤーの移動度、εは誘電率、tは
ゲート絶縁膜の膜厚、Wはゲート幅、Lはゲート長。)
から明らかなようにTPTのON時の電流、及び相互コ
ンダクタンス1mが増大し、TFTの性能が向上する結
果、従来法の例等に比較してより小さい、かつ高性能な
TPTに置換できることを示している。又、液晶を駆動
するために比較的大容盪を必要とする蓄積コンデンサー
の単位面積当りの容量も又増加し、従来法の例等に比較
してより小さい形成面積でよいことを示している。
This means that the TFT performance index (μ°ε/l-”/L)
(Here, μ is the carrier mobility, ε is the dielectric constant, t is the thickness of the gate insulating film, W is the gate width, and L is the gate length.)
As is clear from the above, the current when the TPT is turned on and the mutual conductance 1m increase, and the performance of the TFT improves, indicating that it can be replaced with a smaller and higher performance TPT compared to the conventional method. ing. In addition, the capacitance per unit area of the storage capacitor, which requires a relatively large capacity to drive the liquid crystal, also increases, indicating that a smaller area is required compared to conventional methods. .

一方マトリクス型液晶表示等の画!i!表示ではその解
像度の制約から単位画素の最大寸法は、約800 tク
ロメ−ドル0以下程度に小さくする必要がある。
On the other hand, images such as matrix type liquid crystal display! i! In displaying, the maximum size of a unit pixel must be reduced to about 800 t chromedore 0 or less due to resolution constraints.

以上に説明しt二ように、この発明に上ればTPT等能
動素子の設置面積が小さく、表示電極の設置面積が増大
できる結果1.、、表示性能の目安となる開fllll
l1 目串が増大できると共に、蓄積コンデンサーが小面積で
形成可能となり、良好な表示品質を有するマトリクス型
液晶表示装置が得らnる。又低温プロセスで製造できる
ので安価なガラス基板等の使用が可能となり、大画面の
マトリクス型液晶表示装ばか得らnる効果がある。
As explained above, according to the present invention, the installation area of active elements such as TPT is small and the installation area of display electrodes can be increased.1. ,,opening which is a guideline for display performance
11 The number of meshes can be increased, and the storage capacitor can be formed in a small area, so that a matrix type liquid crystal display device with good display quality can be obtained. In addition, since it can be manufactured using a low-temperature process, it is possible to use inexpensive glass substrates, etc., and this has the advantage of producing a large-screen matrix-type liquid crystal display device.

【図面の簡単な説明】[Brief explanation of the drawing]

誦1図はTFTアレイの構成を説明するための図、第2
図はマトリクス型液晶表示装置の断面構造図、第8図は
従来のτFTアレイパ画素の部分平面内、第4図は第8
図ト■線における断面構造図、第6図はこの発明の一実
施例のTFTアレイ画素の部分平面図、第6図は第6図
w−wmにおける断面構造図である。 図において、(1)はゲート縁、Mは蓄積コンデンサー
電極、(ト)はゲート絶縁lal!!、aηは誘電体で
ある。 なお、図中同一符号はそ口ぞれ同一、又は相当部分を示
す。 代理人 葛PR信−(外1名) 第1図 σ 第2図 第3図 第4図 β 第5図 第6図 θ 1、事件の表示    特願昭511−19115!1
1号3、補正をする者 5、 1ill正の対象 明細書の発明の詳細な説明の欄 6、  @正の内容 (1)明細書をつぎのとおり訂正する。
Recitation Figure 1 is a diagram for explaining the configuration of the TFT array, Figure 2 is a diagram for explaining the configuration of the TFT array.
The figure is a cross-sectional structural diagram of a matrix type liquid crystal display device, FIG. 8 is a partial plane of a conventional τFT array pixel, and FIG.
FIG. 6 is a partial plan view of a TFT array pixel according to an embodiment of the present invention, and FIG. 6 is a cross-sectional structural diagram taken along line wwm in FIG. In the figure, (1) is the gate edge, M is the storage capacitor electrode, and (G) is the gate insulation lal! ! , aη are dielectrics. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent: Katsura PR letter - (1 other person) Figure 1 σ Figure 2 Figure 3 Figure 4 Figure β Figure 5 Figure 6 θ 1. Indication of incident Patent application 1987-19115!1
No. 1, No. 3, Person making the amendment 5, 1ill Detailed explanation of the invention in the correct subject specification column 6, @Correct contents (1) The description is corrected as follows.

Claims (1)

【特許請求の範囲】[Claims] (1)複数個のゲート線、これらのゲート線と直交する
複数個のソース線、こnらのゲート線とソース線の交点
にそnぞれ薄膜トランジスタ(以下TPTと称する)等
の能動素子と信号蓄積コンデンサー等よりなるTFTア
レイが配設された基板と。 透明尋電膜と赤、縁、青等のカラーフィルタ等とが形成
された対向基板との間に液晶を挾持し、上記TFTアレ
イとこnに対向せるカラーフィルタとで単位画素を構成
するマトリクス型液晶表示装置において、上記TFTア
レイのゲート電極、及び蓄積コンデンサー電極材料がT
iで、ゲート絶縁族及び蓄積コンデンサーの誘電体がT
ie、で形成さ口ている仁とを特徴とするマトリクス型
液晶表示装置。
(1) A plurality of gate lines, a plurality of source lines orthogonal to these gate lines, and an active element such as a thin film transistor (hereinafter referred to as TPT) at each intersection of these gate lines and source lines. A substrate on which a TFT array consisting of a signal storage capacitor, etc. is arranged. A matrix type in which a liquid crystal is sandwiched between a transparent transducer film and a counter substrate on which color filters such as red, edge, blue, etc. are formed, and a unit pixel is constituted by the color filter facing the TFT array. In the liquid crystal display device, the gate electrode of the TFT array and the storage capacitor electrode material are T
i, the gate insulator group and the storage capacitor dielectric are T
A matrix type liquid crystal display device characterized by an opening formed by an ie.
JP56193526A 1981-11-28 1981-11-28 Matrix type liquid crystal display Pending JPS5893090A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56193526A JPS5893090A (en) 1981-11-28 1981-11-28 Matrix type liquid crystal display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56193526A JPS5893090A (en) 1981-11-28 1981-11-28 Matrix type liquid crystal display

Publications (1)

Publication Number Publication Date
JPS5893090A true JPS5893090A (en) 1983-06-02

Family

ID=16309533

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56193526A Pending JPS5893090A (en) 1981-11-28 1981-11-28 Matrix type liquid crystal display

Country Status (1)

Country Link
JP (1) JPS5893090A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63148239A (en) * 1986-12-12 1988-06-21 Nec Corp Active matrix type liquid crystal display device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63148239A (en) * 1986-12-12 1988-06-21 Nec Corp Active matrix type liquid crystal display device

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