JPS5890780A - Input protection device - Google Patents
Input protection deviceInfo
- Publication number
- JPS5890780A JPS5890780A JP56188786A JP18878681A JPS5890780A JP S5890780 A JPS5890780 A JP S5890780A JP 56188786 A JP56188786 A JP 56188786A JP 18878681 A JP18878681 A JP 18878681A JP S5890780 A JPS5890780 A JP S5890780A
- Authority
- JP
- Japan
- Prior art keywords
- input
- input protection
- capacity
- wiring
- external lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 238000009792 diffusion process Methods 0.000 claims description 10
- 230000005669 field effect Effects 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 2
- 239000002001 electrolyte material Substances 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 abstract description 2
- 239000000126 substance Substances 0.000 abstract 3
- 230000001419 dependent effect Effects 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000000605 extraction Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 241000270666 Testudines Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000008280 blood Substances 0.000 description 1
- 210000004369 blood Anatomy 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000002305 electric material Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Amplifiers (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Protection Of Static Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明に半導体装置の入力保護装置に関するものである
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input protection device for a semiconductor device.
1#!3縁ゲート亀界効来トランジスタ(以下MO8I
ll rと略記す。)からなる半導体装置において、外
部引き出し電極と入力MO8Trのゲー)1i1:極を
接続する場合、静電気勢による過大電圧が外部端子に印
加されることにより人力MO8Trのゲート絶縁膜が破
壊される恐れがある。これを防ぐため、通常外部引き出
し一極と前記ゲート電極間に保−回路が設けられる。1#! Three-edge gate turtle field effect transistor (hereinafter referred to as MO8I)
It is abbreviated as llr. ), when connecting the external extraction electrode and the gate (1i1) pole of the input MO8Tr, there is a risk that the gate insulating film of the manually operated MO8Tr will be destroyed due to excessive voltage due to static electricity being applied to the external terminal. be. To prevent this, a protection circuit is usually provided between the external lead-out pole and the gate electrode.
Nチャンネル型MO8Trを例にして従来最も一般に用
いられている入力保護装置の平面図を第1図(Jllに
、また、第1図(b)に第1図(a)中に示されるA−
A’の断面図を示す。第2図に第1図に示された入力保
護装置の咎価回路を示す。この入力保護装置の動作原理
は、第2図から明らかな様に、抵抗と容IKよ多入力端
子に加えられた過大を圧波形を遅延させてなめらかにし
、かつ拡散層と基板間のダイオードの順・逆方向特性を
利用し、入力正過犬亀圧は逆方向降伏電圧に、入力食過
大電圧はダイオードの順方向電圧におさえるものである
。Taking an N-channel type MO8Tr as an example, a plan view of the most commonly used input protection device in the past is shown in FIG.
A sectional view of A' is shown. FIG. 2 shows a value circuit of the input protection device shown in FIG. 1. As is clear from Figure 2, the operating principle of this input protection device is to delay the pressure waveform to smooth out the excessive resistance and capacitance IK applied to the multi-input terminal, and to smooth out the pressure waveform of the diode between the diffusion layer and the substrate. By using the forward and reverse characteristics, the input positive overvoltage is suppressed to the reverse breakdown voltage, and the input excessive voltage is suppressed to the forward voltage of the diode.
ところが、従来の入力保護装置では、保験回路の容重と
して、前記拡散層と半導体基板間に生ずる接合谷tを用
りているため、入力端子に印加される−圧が高いほど接
合部の空乏層は大きく広が9、接曾谷′lIiは小さく
なる。よって、従来の入力保護回路では入力端子に印加
される電圧が筒いtよと波形を遅延δぜる能力が低下し
、入力保護の能力か劣化するという欠点があり、非常に
不都合であった。However, in conventional input protection devices, the junction valley t generated between the diffusion layer and the semiconductor substrate is used as the capacity of the guarantee circuit, so the higher the voltage applied to the input terminal, the more depleted the junction becomes. The layer widens 9 and the contact valley 'lIi becomes smaller. Therefore, in conventional input protection circuits, the ability to delay the waveform of the voltage applied to the input terminal decreases as the voltage applied to the input terminal increases, resulting in a deterioration of the input protection ability, which is very inconvenient. .
本発明は、上記従来の欠点の無い入力保護回路を提供す
るものである。The present invention provides an input protection circuit that does not have the above-mentioned conventional drawbacks.
本発明は、−導t/1.型半導体基板に形成された逆導
電型拡散層を入力用外部引き出し一極と入力絶縁グー)
’m界効釆トランジスタのゲート電極間に設けた入力保
護回路において前記入力用外部引き出し電極とim m
c逆導kW拡散−間に設けらnた配線上に他の領域の誘
電体物質よシもよシ大きな心電率をMする@電体物質を
設置したことを%徴とするO
次に′2#−兜明の一実施例を図面を用いて説明する。The present invention provides - conduction t/1. A reverse conductivity type diffusion layer formed on a type semiconductor substrate is connected to an external lead-out single pole for input and an input insulation group)
In the input protection circuit provided between the gate electrode of the field effect transistor, the input external extraction electrode and im
c Reverse conduction kW diffusion - % sign of the installation of an electric material that has a larger electrocardial rate than dielectric materials in other areas on the wiring placed between n Next An embodiment of '2#-Kabutomei will be described with reference to the drawings.
第3図(a)は本発明実施例の平面図、第3図(b)は
第3図(!L)OB−B’の断血図である。第4図は第
3図の寺伽回路図−でるる。従来の写^蝕刻、熱拡散、
気相成長及び金輌配組技術を用いて第3図に示す構造の
入力保護装置ができる。入力用外部引き出し/#jIL
極15と半導体基板と逆導電型拡散層12の間に設けら
れた配線の一部分の下に、たとえば窒化珪素16のよう
に、周囲の酸化膜よりもよシ大きな@電率をもつ誘電体
物質を設置することによって、第4図の容1207を付
加したものである。FIG. 3(a) is a plan view of the embodiment of the present invention, and FIG. 3(b) is a blood cut diagram of FIG. 3(!L) OB-B'. Figure 4 is the Teragawa circuit diagram of Figure 3. Conventional photoetching, thermal diffusion,
An input protection device having the structure shown in FIG. 3 can be produced using vapor phase growth and metal deposition techniques. External input drawer/#jIL
Under a part of the wiring provided between the electrode 15, the semiconductor substrate, and the reverse conductivity type diffusion layer 12, a dielectric material having a higher electric constant than the surrounding oxide film, such as silicon nitride 16, is placed. By installing this, the capacity 1207 in FIG. 4 is added.
第3図では示していないが、該容量は異穐の訪一体物質
を多層構造状に設置することによっても付加できること
は明らかである。Although not shown in FIG. 3, it is clear that the capacity can also be added by arranging the heterogeneous visiting materials in a multi-layered structure.
本発明における入力保護回路の動作原理は、従来の入力
保護回路とほぼ同じであるが、第4図に示す逼り、外部
引き出し電極201から拡散層202の配線に入力端子
に印加させる電圧に依存しない容量207が設置されて
いる為、スパイク状の入力過電圧が入力端子201に印
加されても容重による遅延でなめらかKなシ従来の入力
保護回路よシも入力保護としての機能を高める効果があ
る。また谷蓋207は第4図の拡散層202とゲート電
極205の間に設置するよシも、本特許の如く外部引き
出し電極201と拡散層202の間に設置した方が効果
が大である。The operating principle of the input protection circuit according to the present invention is almost the same as that of the conventional input protection circuit. Since the capacitor 207 is installed, even if a spike-like input overvoltage is applied to the input terminal 201, the delay due to the capacitance and weight will be smooth.This has the effect of enhancing the input protection function compared to conventional input protection circuits. . Further, although the valley cover 207 is installed between the diffusion layer 202 and the gate electrode 205 as shown in FIG. 4, it is more effective if it is installed between the external extraction electrode 201 and the diffusion layer 202 as in this patent.
筐た、第3図には記入しなかったが、容量207を設け
る領域の基板表面に基板と四導電型で基板よシも一磯に
の不純物を設けるとさらに効果は大きくなる。Although not shown in FIG. 3, the effect will be even greater if an impurity of four conductivity types is provided on the surface of the substrate in the region where the capacitor 207 is provided, and is located on the same side as the substrate.
以上は、Nチャンネルアルミニウムグー)MO8T r
′?を例に説明したが、他のいかなる形成のMO8T
rにも適用が可能であることは明らかである。The above is N-channel aluminum goo) MO8T r
′? Although the explanation was given using MO8T as an example, any other formation of MO8T
It is clear that this can also be applied to r.
第1図(a)および(b)は従来の入力保護回路の平面
図およびA−A’の断面図、第2図はその等価回路図、
第3図(a)および(b)は本発明の一実施例の平面図
および13−B’の断面図、第4図はその勢価回路図、
でめる。
なお囚において、1.11・・・・・・P型半導体基板
、2.12・・・・・・N型半導体基板% 13・・・
・・・窒化#i素、4.14・・・・・・接続用穴、5
.15・・・・・・外部引き出しアルミ電極、5’、1
5’・・・・・・MOS Trのゲート電極へのアル
ミニウム配線、101,102・・・・・・入力端子、
102,202,106.206・・・・・・抵抗、1
03.203,207・・・・・・容量、104,20
4・・・・・・ダイオード、105.205−・・・・
入力MO8Tr。
である。FIGS. 1(a) and (b) are a plan view and a sectional view taken along line A-A' of a conventional input protection circuit, and FIG. 2 is an equivalent circuit diagram thereof.
3(a) and (b) are a plan view and a sectional view taken along line 13-B' of an embodiment of the present invention, FIG. 4 is a circuit diagram thereof,
Demeru. In addition, 1.11...P-type semiconductor substrate, 2.12...N-type semiconductor substrate% 13...
...Nitride #i element, 4.14... Connection hole, 5
.. 15...External lead-out aluminum electrode, 5', 1
5'... Aluminum wiring to the gate electrode of MOS Tr, 101, 102... Input terminal,
102,202,106.206...Resistance, 1
03.203,207... Capacity, 104,20
4...Diode, 105.205-...
Input MO8Tr. It is.
Claims (1)
用外部引き出し電極と入力絶縁ゲート電界効果トランジ
スタのゲート′IL極間に設けた入力保護装置において
、前記入力用外部側き出し一極と前記逆導電型拡散層間
に設けられた配線下に他の領域の酩亀体物質よりもより
大きな防電率をゼするi%t&体物負を設置したことt
特徴とする入力保護装置。In an input protection device in which a reverse conductivity type diffusion layer formed on a single-conducting turtle-type semiconductor substrate is provided between an input external lead electrode and a gate 'IL electrode of an input insulated gate field effect transistor, the input external side lead electrode Under the wiring provided between the pole and the opposite conductivity type diffusion layer, a material having a higher electrical resistance than the electrolyte material in other areas is installed.
Features an input protection device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56188786A JPS5890780A (en) | 1981-11-25 | 1981-11-25 | Input protection device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56188786A JPS5890780A (en) | 1981-11-25 | 1981-11-25 | Input protection device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5890780A true JPS5890780A (en) | 1983-05-30 |
Family
ID=16229763
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56188786A Pending JPS5890780A (en) | 1981-11-25 | 1981-11-25 | Input protection device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5890780A (en) |
-
1981
- 1981-11-25 JP JP56188786A patent/JPS5890780A/en active Pending
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