JPS5887942A - チヤネル多重化方式 - Google Patents

チヤネル多重化方式

Info

Publication number
JPS5887942A
JPS5887942A JP18441581A JP18441581A JPS5887942A JP S5887942 A JPS5887942 A JP S5887942A JP 18441581 A JP18441581 A JP 18441581A JP 18441581 A JP18441581 A JP 18441581A JP S5887942 A JPS5887942 A JP S5887942A
Authority
JP
Japan
Prior art keywords
channel
data
transmission
written
terminal station
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18441581A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0124382B2 (enrdf_load_stackoverflow
Inventor
「かい」田　喜基
Yoshimoto Aida
Eiji Tange
丹下　栄二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP18441581A priority Critical patent/JPS5887942A/ja
Publication of JPS5887942A publication Critical patent/JPS5887942A/ja
Publication of JPH0124382B2 publication Critical patent/JPH0124382B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Small-Scale Networks (AREA)
JP18441581A 1981-11-19 1981-11-19 チヤネル多重化方式 Granted JPS5887942A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18441581A JPS5887942A (ja) 1981-11-19 1981-11-19 チヤネル多重化方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18441581A JPS5887942A (ja) 1981-11-19 1981-11-19 チヤネル多重化方式

Publications (2)

Publication Number Publication Date
JPS5887942A true JPS5887942A (ja) 1983-05-25
JPH0124382B2 JPH0124382B2 (enrdf_load_stackoverflow) 1989-05-11

Family

ID=16152763

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18441581A Granted JPS5887942A (ja) 1981-11-19 1981-11-19 チヤネル多重化方式

Country Status (1)

Country Link
JP (1) JPS5887942A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6434034A (en) * 1987-07-30 1989-02-03 Mirai Bill Kenkyu Kaihatsu Kk Data terminal selection system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6434034A (en) * 1987-07-30 1989-02-03 Mirai Bill Kenkyu Kaihatsu Kk Data terminal selection system

Also Published As

Publication number Publication date
JPH0124382B2 (enrdf_load_stackoverflow) 1989-05-11

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