JPS5880875A - Constant-voltage diode for semiconductor integrated circuit - Google Patents
Constant-voltage diode for semiconductor integrated circuitInfo
- Publication number
- JPS5880875A JPS5880875A JP18009881A JP18009881A JPS5880875A JP S5880875 A JPS5880875 A JP S5880875A JP 18009881 A JP18009881 A JP 18009881A JP 18009881 A JP18009881 A JP 18009881A JP S5880875 A JPS5880875 A JP S5880875A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- diffusion layer
- diffused
- silicon substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 239000012535 impurity Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 17
- 239000010703 silicon Substances 0.000 claims abstract description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 238000009792 diffusion process Methods 0.000 claims description 69
- 239000004020 conductor Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 4
- 238000002955 isolation Methods 0.000 abstract description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract description 2
- 229910052757 nitrogen Inorganic materials 0.000 abstract description 2
- 239000001301 oxygen Substances 0.000 abstract description 2
- 229910052760 oxygen Inorganic materials 0.000 abstract description 2
- 238000000926 separation method Methods 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はトランジスタ等のＰＮ接合の逆方向特性を利用
した半導体集積回路用定電圧ダイオードに関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a constant voltage diode for semiconductor integrated circuits that utilizes the reverse characteristics of a PN junction such as a transistor.
シリコントランジスタのＰＮ接合の逆方向特性が定電圧
ダイオードの特性に近いものであることはすでに知られ
ているところであり、この特性を利用して定電圧ダイオ
ードを得ようとすることもなされている。ところで半導
体集積回路では、定電圧ｉ′得るために該回路内に定電
圧ダイオードを作り込むことが要求されており、この定
電圧ダイオードを半導体集積回路中に作ろうとする場合
は、一般にトランジスタのペース・エミッタ接合の逆方
向ブレークダウン電圧が利用される。It is already known that the reverse characteristics of the PN junction of a silicon transistor are close to those of a constant voltage diode, and attempts have been made to utilize this characteristic to obtain a constant voltage diode. By the way, in semiconductor integrated circuits, it is required to create a constant voltage diode in the circuit in order to obtain a constant voltage i', and when trying to create this constant voltage diode in a semiconductor integrated circuit, it is generally necessary to・The reverse breakdown voltage of the emitter junction is utilized.
しかしながら半導体集積回路におけるトランジスタの基
本的な構造はプレーナ構造であり、 ＰＮ接合の端部は
表置保護被膜直下の基板表面に存在し、しかもトランジ
スタの拡散領域は全て表面からの拡散によって形成され
ているため、基板表面に近いほど不純物濃度が高く、こ
のため表面に位置するＰＮ接合部分の不純物濃度の勾配
は大きく、ＰＮ接合のブレークダウンは表面近傍におい
て起る。この場合表面における結晶の不整合あるいは汚
れなどにより最も弱い部分から順次スポット状にブレー
クダウンを起こすのが昔通であり、一様なブレークダウ
ンが起こりにくい。この現象は定電圧ダイオードの発振
、静特性での折れ曲がり、あるいはソフトブレークダウ
ンの原因になる゛のみならず定電圧ダイオードの劣化に
もつながるものである。However, the basic structure of a transistor in a semiconductor integrated circuit is a planar structure, and the end of the PN junction exists on the substrate surface directly under the surface protective film, and the diffusion region of the transistor is entirely formed by diffusion from the surface. Therefore, the closer to the substrate surface the higher the impurity concentration is, and therefore the gradient of the impurity concentration at the PN junction located on the surface is large, and breakdown of the PN junction occurs near the surface. In this case, it has traditionally been the case that breakdown occurs in spots starting from the weakest part due to crystal mismatch or dirt on the surface, and uniform breakdown is difficult to occur. This phenomenon not only causes oscillation of the voltage regulator diode, bending due to static characteristics, or soft breakdown, but also leads to deterioration of the voltage regulator diode.
また従来のトランジスタのＰＮ接合の逆方向特性を利用
した定電圧ダイオードでは、表面の影響を直接受けるた
め、表面単位や表面保護膜中のキャリアトラップに起因
する雑音が発生し、低雑音を要求される半導体集積回路
には使用することができない。In addition, in a constant voltage diode that utilizes the reverse characteristics of the PN junction of a conventional transistor, it is directly affected by the surface, so noise is generated due to carrier traps in the surface unit and the surface protective film, and low noise is required. It cannot be used for semiconductor integrated circuits.
この発明は以上のような従来の問題点に鑑みてなされた
もので、Ｐ型シリコン基板上にＮ型高不純物濃度の埋込
拡散層を、該埋込拡散層上にＰ型高不純物濃度の第１の
拡散層をそれぞれ形成し、両拡散層をエピタキシャル層
によって被覆し、該エピタキシャル層を貫通して上記第
１の拡散層とＰＮ接合のダイオードを形成するＮ型高不
純物濃度の第２の拡散層を設けることにより、従来の半
導体集積回路の基本的な製造工程を変更することなく、
該回路丙において良好な定電圧特性が得られるようにし
た半導体集積回路用定電圧ダイオードを提供することを
目的としている。This invention was made in view of the conventional problems as described above, and includes an N-type buried diffusion layer with a high impurity concentration on a P-type silicon substrate, and a P-type high impurity concentration buried diffusion layer on the buried diffusion layer. A first diffusion layer is formed respectively, both diffusion layers are covered with an epitaxial layer, and an N-type high impurity concentration second diffusion layer is formed by penetrating the epitaxial layer and forming a PN junction diode with the first diffusion layer. By providing a diffusion layer, the basic manufacturing process of conventional semiconductor integrated circuits can be made without changing.
It is an object of the present invention to provide a constant voltage diode for a semiconductor integrated circuit that allows good constant voltage characteristics to be obtained in the circuit.
以下本発明の一実施例を図について説明する。An embodiment of the present invention will be described below with reference to the drawings.
第１図及び第２図は本発明の一実施例による半導体集積
回路用定電圧ダイオードを示し、第１図は本定電圧ダイ
オードの製作工程途中の断面図、第２図は本定電圧ダイ
オードの断面図である。第２図に右いて、（１）はＰ型
シリコン基板、（２）はこのシリコン基板（１）上に選
択的に形成されたＮ型高不純物濃度の埋込拡散層、（３
）はこの埋込拡散層（２）上に該拡散層（２）の内側に
位置しかつ上記シリコン基板（１）に達しないようにし
て形成され、埋込拡散層（２）とＰＮ接合を形成するＰ
型高不純物濃度の第１の拡散層、（４）はシリコン基板
（１）上に形成されたＰ型高不純物濃度の下方浮き上り
分離拡散層である。1 and 2 show a voltage regulator diode for semiconductor integrated circuits according to an embodiment of the present invention, FIG. 1 is a sectional view of the voltage regulator diode in the middle of the manufacturing process, and FIG. 2 is a sectional view of the voltage regulator diode. FIG. On the right side of FIG. 2, (1) is a P-type silicon substrate, (2) is an N-type buried diffusion layer with a high impurity concentration selectively formed on this silicon substrate (1), and (3) is a buried diffusion layer with high impurity concentration.
) is formed on this buried diffusion layer (2) so as to be located inside the diffusion layer (2) and not to reach the silicon substrate (1), and forms a PN junction with the buried diffusion layer (2). forming P
The first diffusion layer (4) with high impurity concentration is a downwardly floating isolation diffusion layer with high P-type impurity concentration formed on the silicon substrate (1).
また（５）は上記シリコン基板（１）１番こ上記拡散層
（２）＋３＋ ＋４１を覆って形成されたＮｆｉのエピ
タキシャル層、（６）はこのエピタキシャルＩＩ １５
）内に上下方向に設けられ、上記第１の拡散層（３）の
一部と重なり合って該拡散層（３）とＰＮ接合のダイオ
ードを形成するＮ型高不純物濃度の第２の拡散層、（７
）はエピタキシャル−（５）内に上下方阻に形成され、
上記第１の拡散層（３）と上記ダイオード部以外で重な
り合うＰ型の高不純物濃度の第３の拡散層、（８）はエ
ピタキシャル層（５）内に上下方向に形成され、上記分
離拡散層（４）と重なり合うＰ型高不純物濃度の分離拡
散層である。さらに（９）はシリコン酸化膜、（１０１
）（１０ｂ）は酸化膜（９）上に上記第２．第３の拡散
層ｔ６１ ｔｅｌと接続して形成されたカソード電極及
びアノード電極である。Further, (5) is an Nfi epitaxial layer formed covering the first diffusion layer (2) +3+ +41 of the silicon substrate (1), and (6) is this epitaxial layer II 15.
) a second diffusion layer with a high impurity concentration of N-type, which is provided in the vertical direction within the region and overlaps a part of the first diffusion layer (3) to form a PN junction diode with the diffusion layer (3); (7
) is formed vertically in the epitaxial layer (5),
A P-type high impurity concentration third diffusion layer (8) overlapping with the first diffusion layer (3) in areas other than the diode portion is formed vertically within the epitaxial layer (5), and is formed as the separation diffusion layer. This is a P-type high impurity concentration separation diffusion layer overlapping with (4). Furthermore, (9) is a silicon oxide film, (101
) (10b) is the above-mentioned second. A cathode electrode and an anode electrode are formed in connection with the third diffusion layer t61 tel.
次に本実施例定電圧ダ〉イオードの製作方法を説明する
。Next, a method of manufacturing the constant voltage diode of this embodiment will be explained.
まずＰ型シリコン基板（１）に通常、埋込拡散層といわ
れるＮ型の高濃度拡散層（２）を選択的に形成し、この
埋込拡散層（２）上にこれをはみ出さないようにして高
濃度のＰ全不純物拡散層（３）を形成するとともに、分
離拡散領域の基板（１）との重ね令せ領域にも同時に拡
散させて高濃度のＰ型下方浮き上り分離拡散層（４）を
形成する。この状態で熱処理を行ない、基板（１）上に
各拡散層＋２１ ＋３１１４１を覆ってエピタキシャル
層（５）を成長させる。すると埋込拡散層（２）及び’
！！！１１ｉ６一度不純物層（３）はＩｊｉ１図に示す
ようにエピタキシャル層（６）内に浮き上がった状態と
なる。First, an N-type high-concentration diffusion layer (2), usually called a buried diffusion layer, is selectively formed on a P-type silicon substrate (1), and the layer is careful not to protrude onto the buried diffusion layer (2). In addition to forming a high concentration P-type full impurity diffusion layer (3), it is also simultaneously diffused into the overlapping region of the separation diffusion region with the substrate (1) to form a high concentration P-type downward floating separation diffusion layer (3). 4) Form. Heat treatment is performed in this state to grow an epitaxial layer (5) on the substrate (1) covering each diffusion layer +21 +31141. Then, the buried diffusion layer (2) and '
! ! ! 11i6 Once the impurity layer (3) is in a floating state within the epitaxial layer (6) as shown in Figure Iji1.
そしてエピタキシャル層（５）の表面にシリコン酸化膜
（９）を生成し、この酸化膜（９）によく知られている
写真食刻技術を用いて選択的に開孔を行ない、その孔番
ζ順にＰ全不純物拡散層（７ｍ）（８ｍ）及びＮ
゛型拡散層（６＆）をそれぞれ形成し、これによって
素子は第１図に示す構造となる。Then, a silicon oxide film (9) is formed on the surface of the epitaxial layer (5), and holes are selectively formed in this oxide film (9) using a well-known photolithography technique. In order, P full impurity diffusion layer (7m) (8m) and N
A type diffusion layer (6&) is formed, and the device has the structure shown in FIG. 1.
次にこの素子を１０００℃〜１１００℃の高温の窒素又
は酸素雰囲気中で熱処理する。すると拡散層（６ａ）（
７ｍ）はＰ型拡散浮き上がり層（３）に、拡散層（８１
りはＰ型分離拡散層（４）にそれぞれ拡散して重なり合
うようになり、これによって第２図に示すような第２．
第３の拡散ＩＩＩ ｔ６） １７）及び分離拡散層（８
）が形成される。このときＮ型エピタキシャル層（５）
はＰ全波散層ｆ４） （８）によって電気的に分離され
、該エピタキシャル層（５）には島領域が形成される。Next, this element is heat treated in a nitrogen or oxygen atmosphere at a high temperature of 1000°C to 1100°C. Then, the diffusion layer (6a) (
7m) is a P-type diffused floating layer (3), and a diffusion layer (81
The particles diffuse into the P-type isolation diffusion layer (4) and overlap each other, thereby forming a second layer as shown in FIG.
Third diffusion III t6) 17) and separation diffusion layer (8
) is formed. At this time, the N-type epitaxial layer (5)
is electrically isolated by a P full wave dissipation layer f4) (8), and an island region is formed in the epitaxial layer (5).
これは通常、分離拡散として知られているものである。This is commonly known as separation diffusion.
そして最後に写真食刻技術によって酸化膜（９）に電極
を取り出すためのコンタクト部を開孔し、金員配線を行
って電極（１ｏａ）（１ｏｂ）を形成する。Finally, a contact portion for taking out the electrode is opened in the oxide film (9) by photolithography, and metal wiring is performed to form the electrode (1oa) (1ob).
以上のような本実施例の定電圧ダイオードでは、Ｎ型拡
散ｍ（６）の不純物一度がエピタキシャル層（５）に比
べて十分に大きいため、ＰＮ接合の逆方向ブレークダウ
ンはエピタキシャル層（５）内の接合面面で起こり、表
面の影響を全く受けず、その結果安定しただ電圧特性が
得られ、又低雑音素子として半導体集積回路の中に組み
込むことができる。またダイオードを形成するＰ型高濃
度拡散４（３）はＮ型拡散層（２）上に位置し、基板（
１）からは電気約６こ分離されているので、拡散層＋６
１１７１によって電極（１０１）（１０ｂ）を表面から
容易に取り出すことができる。In the constant voltage diode of this example as described above, since the impurity concentration in the N-type diffusion m(6) is sufficiently larger than that in the epitaxial layer (5), the reverse breakdown of the PN junction occurs in the epitaxial layer (5). This occurs at the inner junction surface and is completely unaffected by the surface, resulting in stable voltage characteristics and can be incorporated into a semiconductor integrated circuit as a low-noise element. Furthermore, the P-type high concentration diffusion layer 4 (3) forming the diode is located on the N-type diffusion layer (2), and the substrate (
Since it is approximately 6 electrically separated from 1), the diffusion layer +6
1171 allows the electrodes (101) (10b) to be easily taken out from the surface.
また本発明の定電圧ダイオードは、既存のシリコンを基
板とする半導体集積回路の製造工程になんら新しい工程
を追加することなく形成できる。Further, the constant voltage diode of the present invention can be formed without adding any new process to the existing manufacturing process of semiconductor integrated circuits using silicon as a substrate.
それは、拡散層（２）は他の埋込層を形成する際に、拡
散層＋３） ＋４１は下方浮き上り分離層を形成する際
にそれぞれ形成でき、又拡散層（７） （８１は表面か
らの分離拡散層であり、さらに拡散層（６）は通常、コ
レクタウオールと呼ばれる拡散層を形成するときにでき
るからである。The diffusion layer (2) can be formed when forming another buried layer, the diffusion layer +3) +41 can be formed when forming a downwardly floating separation layer, and the diffusion layer (7) (81 can be formed from the surface). This is because the diffusion layer (6) is usually formed when forming a diffusion layer called collector all.
以上のように本発明に係る半導体集積回路用定電圧ダイ
オードによれば、Ｎ型の高不純物濃度の埋込拡散層上に
形成したＰ型の高不純物濃度の第１の拡散層とＰＮ接合
のダイオ−ｔを形成するＮ型の高不純物濃度の第一の拡
散層を、上記埋込拡散層と第１の拡散層とを覆うエピタ
キシャル層を貫通させて形成したので、従来の半導体集
積回路の基本的な製造工程に変更をもたらすことなく、
該回路内に良好な定電圧特性を有する定電圧ダイオード
を作ることができ、その工業的価値は大きい０As described above, according to the voltage regulator diode for semiconductor integrated circuits according to the present invention, the first diffusion layer with high impurity concentration of P type formed on the buried diffusion layer with high impurity concentration of N type and the PN junction The N-type first diffusion layer with a high impurity concentration that forms the diode T is formed by penetrating the epitaxial layer that covers the buried diffusion layer and the first diffusion layer, so that it is possible to without changing the basic manufacturing process.
It is possible to create a constant voltage diode with good constant voltage characteristics in the circuit, and its industrial value is 0.
第１図は本発明の一実施例による半導体集積回路用定電
圧ダイオードの製造工程途中に初ける断面図、第２図は
上記定電圧ダイオードの断面図である。
（１）・・・シリコン基板、（２）・・・埋込拡散層、
（３）・・・第１の拡散層、（５）・・・エピタキシャ
ル層、（６）・・・第２の拡散層、（７）・・・第３の
拡散層、（１０ａ）（１０ｂ）・・電極。
代理人 葛 野 信 −
第１図
第２図
手続補正書（自発）
昭和５７年１０月 ６日
２、発明の名称 半導体集積回路用
定電圧ダイオード
３、補正をする者
６、 捕止の内容
明細書をつぎのとおり訂正する。
（２）FIG. 1 is a sectional view taken during the manufacturing process of a voltage regulator diode for a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 is a sectional view of the voltage regulator diode. (1)...Silicon substrate, (2)...Buried diffusion layer,
(3)...First diffusion layer, (5)...Epitaxial layer, (6)...Second diffusion layer, (7)...Third diffusion layer, (10a) (10b )··electrode. Agent Makoto Kuzuno - Figure 1 Figure 2 Procedural amendment (voluntary) October 6, 1982 2, Title of invention: Constant voltage diode for semiconductor integrated circuits 3, Person making the amendment 6, Details of arrest The text is corrected as follows. (2)
Claims (1)
ン基板上に選択的に形成されたＮ型の高不純物濃度の埋
込拡散層と、該埋込拡散層の内側に位置しかつ上記シリ
コン基板に達しないようｋしての高不純物濃度の第１の
拡散層と、上記シリコン基板上に上記埋込拡散層及び第
１の拡散層を覆って形成されたＮ型のエピタキシャル層
と、該エピタキシャル層内に上下方向に設けられ上記第
１の拡散層の一部と重なり合って該第１の輯散層とＰＮ
接合のダイオードを形成するＮ型の高不純物濃度の第２
の拡散層と、上記エピタキシャル層内に上下方同番こ設
けられ上記第１の拡散層と上記ダイオード部以外で重な
り合うＰ型の高不純物濃度の第３の拡散層と、上記エピ
タキシャル層の表面上にそれぞれ形成され上記第２．第
３の拡散層とそれぞれ接続されるカソード電極及びアノ
ード電極とを備えたことを特徴とする半導体集積回路用
定電圧ダイオード。(1) a silicon substrate having a P-type conductor; an N-type buried diffusion layer with a high impurity concentration selectively formed on the silicon substrate; a first diffusion layer with a high impurity concentration so as not to reach the silicon substrate; an N-type epitaxial layer formed on the silicon substrate to cover the buried diffusion layer and the first diffusion layer; The first diffusion layer and the PN are provided in the epitaxial layer in the vertical direction and overlap a part of the first diffusion layer.
A second layer with a high impurity concentration of N type forms a junction diode.
a P-type high impurity concentration third diffusion layer which is provided in the same number above and below in the epitaxial layer and overlaps with the first diffusion layer in areas other than the diode portion; are respectively formed in the above-mentioned second. A constant voltage diode for a semiconductor integrated circuit, comprising a cathode electrode and an anode electrode each connected to a third diffusion layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18009881A JPS5880875A (en) | 1981-11-09 | 1981-11-09 | Constant-voltage diode for semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18009881A JPS5880875A (en) | 1981-11-09 | 1981-11-09 | Constant-voltage diode for semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5880875A true JPS5880875A (en) | 1983-05-16 |
Family
ID=16077390
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18009881A Pending JPS5880875A (en) | 1981-11-09 | 1981-11-09 | Constant-voltage diode for semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5880875A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0314399A2 (en) * | 1987-10-30 | 1989-05-03 | Precision Monolithics Inc. | Buried zener diode and method of forming the same |
| US5986327A (en) * | 1989-11-15 | 1999-11-16 | Kabushiki Kaisha Toshiba | Bipolar type diode |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4829380A (en) * | 1971-08-18 | 1973-04-18 | ||
| JPS5583271A (en) * | 1978-12-20 | 1980-06-23 | Toshiba Corp | Semiconductor device |
-
1981
- 1981-11-09 JP JP18009881A patent/JPS5880875A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4829380A (en) * | 1971-08-18 | 1973-04-18 | ||
| JPS5583271A (en) * | 1978-12-20 | 1980-06-23 | Toshiba Corp | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0314399A2 (en) * | 1987-10-30 | 1989-05-03 | Precision Monolithics Inc. | Buried zener diode and method of forming the same |
| US5986327A (en) * | 1989-11-15 | 1999-11-16 | Kabushiki Kaisha Toshiba | Bipolar type diode |
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