JPS5880564A - Voltage detecting circuit - Google Patents

Voltage detecting circuit

Info

Publication number
JPS5880564A
JPS5880564A JP17946881A JP17946881A JPS5880564A JP S5880564 A JPS5880564 A JP S5880564A JP 17946881 A JP17946881 A JP 17946881A JP 17946881 A JP17946881 A JP 17946881A JP S5880564 A JPS5880564 A JP S5880564A
Authority
JP
Japan
Prior art keywords
voltage
terminal
circuit
transistor
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17946881A
Other languages
Japanese (ja)
Inventor
Seiji Kamata
鎌田 清治
Masao Kayahara
萱原 正雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP17946881A priority Critical patent/JPS5880564A/en
Publication of JPS5880564A publication Critical patent/JPS5880564A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16504Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the components employed
    • G01R19/16519Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the components employed using FET's

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Current Or Voltage (AREA)

Abstract

PURPOSE:To obtain a power voltage drop detecting circuit with low power consumption which is suitable for IC by generating reference voltage by a small number of MOS transistors (TRs) and comparing voltage to be detected with the reference voltage by a complementary MOS type differential amplifier circuit. CONSTITUTION:An active load type differential amplifier circuit 1 is composed of complementary MOS type TRs and voltage is applied to power terminals 2, 3. The gate terminal of a bias MOS TR4 is connected to a terminal 2, for example, so that the TR4 always keeps its connection status. Voltage to be detected is applied to an input terminal 5 and reference voltage to be compared is applied to an input terminal 6. An output terminal 7 outputs voltage similar to the voltage of the terminal 2 when the voltage of the terminal 5 is higher than that of the terminal 6, and outputs voltage similar to that of the terminal 3 when said condition is reversed. A voltage generating circuit 8 outputs the reference voltage to the terminal 6. A PMOSTR 9 connects gate drains in common and the gate an of NMOSTR 10 is connected to the terminal 2, for example, to keep it always at an electrically conducted state.

Description

【発明の詳細な説明】 本発明は電源電圧が低下したことを検出することのでき
る相補MOS型の検出回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a complementary MOS type detection circuit that can detect a drop in power supply voltage.

この種の電圧検出回路を相補MO8型半導体集積回路に
使用する場合、基準となる検出電圧を抵抗分割等で構成
した場合、消費電力を低減するために、高抵抗が必要で
ある。この高抵抗を、たとえば;集積回路内で実現する
ためには、非常に大きな面積となり不都合である。また
基準となる検出電圧を定電圧回路で、構成することもで
きるが、回路構成が複雑となる。
When this type of voltage detection circuit is used in a complementary MO8 type semiconductor integrated circuit and the reference detection voltage is configured by resistor division or the like, a high resistance is required in order to reduce power consumption. In order to realize this high resistance in, for example, an integrated circuit, it would require a very large area, which is disadvantageous. Further, the detection voltage serving as a reference can be configured by a constant voltage circuit, but the circuit configuration becomes complicated.

本発明は、これらの欠点を除去し、少数のMO8型トラ
ンジスタで基準電圧を発生させることによって、低消費
電力の電源電圧降下検出回路を提供するものである。
The present invention eliminates these drawbacks and provides a power supply voltage drop detection circuit with low power consumption by generating a reference voltage with a small number of MO8 type transistors.

以下に本発明の実施例について詳細に説明する。Examples of the present invention will be described in detail below.

第1図は本発明を適用した一実施例であり、1はよく知
られた相補MO8型トランジスタWアクティブロード形
の差動増幅回路であシ、2および3は同回路中の電源端
子である。4は上記差動増幅回路中のバイアス用MO8
型トランジスタであシ、そのゲート端子は該MO8型ト
ランジスタ4が常に導通状態を維持しうるように、例え
ば電源端子2に接続する。6.6は差動増幅回路の入力
端子であり、6には検出したい電圧を印加し、6には比
較すべき基準となる電圧を印加する。7は差動増幅回路
の出力端子で、端子6の入力が端子6の入力より高い場
合は、電源端子2に近い電圧を出力し、端子50入力が
端子60入力より1↓(い場合は、電源端子3に近い電
圧を出力する。8は検出の基準となる電圧を発生させ、
この電圧を上記差動増幅回路1の入力端子6に供給する
だめの電圧発生回路であり、この回路中、9はゲート:
ドレイン両端子を共通接続したPチャネルMO8型トラ
ンジスタで、1oはNチャネルMO8型トランジスタで
あって、このゲートは、該MO8型トランジスタ1oを
常時導通状態に維持しうる直流ゲートバイアスが与えら
れるように、例えば、電源端子2に接続されている。
FIG. 1 shows an embodiment to which the present invention is applied, in which 1 is a well-known complementary MO8 transistor W active load type differential amplifier circuit, and 2 and 3 are power supply terminals in the circuit. . 4 is MO8 for bias in the above differential amplifier circuit.
The gate terminal of the MO8 type transistor 4 is connected to, for example, the power supply terminal 2 so that the MO8 type transistor 4 can always maintain a conductive state. Reference numeral 6.6 is an input terminal of the differential amplifier circuit, to which a voltage to be detected is applied, and to 6 a reference voltage to be compared is applied. 7 is the output terminal of the differential amplifier circuit, and when the input of terminal 6 is higher than the input of terminal 6, it outputs a voltage close to power supply terminal 2, and the input of terminal 50 is 1↓ (if lower than the input of terminal 60, Outputs a voltage close to power supply terminal 3. 8 generates a voltage that is the reference for detection,
This is a voltage generation circuit that supplies this voltage to the input terminal 6 of the differential amplifier circuit 1, and in this circuit, 9 is a gate:
A P-channel MO8 type transistor having both drain terminals connected in common, 1o is an N-channel MO8 type transistor, and this gate is provided with a DC gate bias that can maintain the MO8 type transistor 1o in a conductive state at all times. , for example, is connected to the power supply terminal 2.

この回路構成体8によれば、9.10のトランジスタの
大きさを適当に組み合わせることにより、基準になる電
圧を決めることができる。
According to this circuit structure 8, the reference voltage can be determined by appropriately combining the sizes of the transistors 9.10.

第2図は他の実施例で、1〜7は第1図と同一要素であ
り、検出基準となる電圧を発生する回路8aは、Pチャ
ネルMO8型トランジスター1とNチャネルMO8型゛
トランジスター2で構成され、PチャネルMO3型トラ
ンジスター1が常に導通状態を維持しうるように、その
ゲート端子を例えば電源端子3に接続されている。Nチ
ャネルMO8型トランジスター2は、ゲート、ドレイン
端子を共通接続している。
FIG. 2 shows another embodiment, in which elements 1 to 7 are the same as those in FIG. 1, and a circuit 8a that generates a voltage serving as a detection reference is a P-channel MO8 type transistor 1 and an N-channel MO8 type transistor 2. The gate terminal of the P-channel MO3 type transistor 1 is connected to, for example, a power supply terminal 3 so that the transistor 1 can always maintain a conductive state. The N-channel MO8 type transistor 2 has its gate and drain terminals commonly connected.

第3図は、別の実施例であり、差動増幅回路1′が、前
記第1図示の実施例回路に対比して、NチャネルMO8
型バイアス用トランジスタ4のソース端子13と電源端
子3の間に、NチャネルMO誉 S型トランジスター4を継続接続したものであシ、該ト
ランジスター4のゲート17には制御信号を印加する。
FIG. 3 shows another embodiment, in which the differential amplifier circuit 1' is different from the embodiment circuit shown in FIG.
An N-channel MO/S type transistor 4 is continuously connected between the source terminal 13 of the type bias transistor 4 and the power supply terminal 3, and a control signal is applied to the gate 17 of the transistor 4.

また、基準電圧発生回路8′ も、バイアス用トランジ
スター0のソース端子16と電源端子3との間に、Nチ
ャネルMO8型トランジスタ16を縦続接続しており、
該トランジスタ16のゲートにも、上記MO8型トラン
ジスタ14のゲートへ印加するものと同一の信号を、印
加する。
Further, the reference voltage generation circuit 8' also has an N-channel MO8 type transistor 16 connected in cascade between the source terminal 16 of the bias transistor 0 and the power supply terminal 3.
The same signal applied to the gate of the MO8 type transistor 14 is also applied to the gate of the transistor 16.

この実施例回路によれば、第1図示の例にくらべて消費
電力が低減できる。第4図は、上記第3図示の例のよう
な消費電力低減の回路構成を第2図示の回路例に付加的
に組み入れ、差動増幅回路1′ および基準電圧発生回
路8警を構成したもので、これによれば第2図示のもの
より一段と消費電力低減の効用がある。
According to this embodiment circuit, power consumption can be reduced compared to the example shown in the first diagram. FIG. 4 shows a configuration in which a differential amplifier circuit 1' and a reference voltage generating circuit 8 are constructed by additionally incorporating the circuit configuration for reducing power consumption like the example shown in FIG. According to this, the power consumption can be further reduced than that shown in the second figure.

なお、上述の各実施例回路中、18.19は差動増幅回
路を構成するMO8型トランジスタであり、20.21
は上記各MO8型トランジスタの負荷として作用するM
O8型トランジスタである。。
In each of the above-mentioned example circuits, 18.19 is an MO8 type transistor that constitutes a differential amplifier circuit, and 20.21 is an MO8 type transistor that constitutes a differential amplifier circuit.
is M acting as a load for each MO8 type transistor mentioned above.
It is an O8 type transistor. .

水晶腕時計などのように、小型の電池を電源として使用
する機器においては、その消費電力を極力、低く押える
ことが極めて重要であり、電池より低い電圧を出力でき
る回路例えば容量による電源電圧分圧回路を用い、その
出力で内部の回路を駆動している場合が多い。電池電源
の電圧低下にともなって、この内部回路駆動用の電圧が
低下した時に、水晶発振が停止しないように、電源電圧
値の低下を検出したときは1例えば、電池電圧を直接内
部回路に供給するような、いわゆる、電源切換え手段を
設けることが必要である。
For devices that use small batteries as a power source, such as crystal watches, it is extremely important to keep the power consumption as low as possible. In many cases, the output is used to drive internal circuits. In order to prevent the crystal oscillation from stopping when the voltage for driving this internal circuit decreases due to a decrease in the voltage of the battery power supply, when a decrease in the power supply voltage value is detected, for example, the battery voltage is directly supplied to the internal circuit. It is necessary to provide a so-called power supply switching means.

従って、本発明の電源電圧降下検出回路は上述のような
電源切換え手段と組み合わせることによって、さらに電
池使用上の実効的寿命を引きのばすことが可能であり、
機器の保守を容易にし、一層の長寿命比を図ることがで
きる。
Therefore, by combining the power supply voltage drop detection circuit of the present invention with the power supply switching means as described above, it is possible to further extend the effective life of the battery.
It is possible to facilitate maintenance of the equipment and achieve a longer lifespan.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図ないし第4図の各回路構成は本発明の各実施例で
あり、第1図はPチャネルMO8型トランジスタのゲー
ト、ドレイン端子を接続したアクティブロード形ソース
接地の相補MO8型基準電圧発生回路と、相補MOS型
でアクティブロード形差動増幅器とを接続した電圧検出
回路図、第2図は相補MO8型基準電圧発生回路にNチ
ャネルMO8型トランジスタのゲート、ドレイン端子を
接続したアクティブロード形ソース接地回路を用いた電
圧検出回路図、第3図、第4図は、電流低減用MO8型
トランジスタを接続した電圧検出回路図である。 6・・・・・・被検出入力端子、6・・・・・・検出基
準入力端子、7・・・・・・出力端子、8・・・・・・
検出基準電圧発生回路、9・・・・・・ゲート、ドレイ
ン端子を接続したPチャネルMO8型トランジスタ、1
0゜11・・・・・−バイアス用MO8型トランジスタ
%12・・・・・・ゲ〜ト、ドレイン端子を接続したN
チャネルMO8型トランジスタ、13・・・・・・MO
8型トランジスタ4のソース端子、14.16・・・・
・・制御用MO8型トランジスタ、16・・・・・・ト
ランジスタ16のドレイン端子、17・・・・・・トラ
ンジスタ14および16のゲート端子、18.19・・
・・・NチャネルMO8型トランジスタ、20.21・
・・・PチャネルMO5型トランジスタ。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第3
図 1図 第2図 11n   /
Each of the circuit configurations shown in FIGS. 1 to 4 is an embodiment of the present invention, and FIG. 1 shows a complementary MO8-type reference voltage generator of an active-load type with a common source connected to the gate and drain terminals of a P-channel MO8-type transistor. A voltage detection circuit diagram in which the circuit is connected to a complementary MOS type active load type differential amplifier. Figure 2 is an active load type circuit in which the gate and drain terminals of an N-channel MO8 type transistor are connected to a complementary MO8 type reference voltage generation circuit. FIGS. 3 and 4 are voltage detection circuit diagrams using a common source circuit. FIGS. 3 and 4 are voltage detection circuit diagrams in which an MO8 type transistor for current reduction is connected. 6...Input terminal to be detected, 6...Detection reference input terminal, 7...Output terminal, 8...
Detection reference voltage generation circuit, 9...P-channel MO8 type transistor with gate and drain terminals connected, 1
0゜11...-MO8 type transistor for bias %12...N with gate and drain terminals connected
Channel MO8 type transistor, 13...MO
Source terminal of 8 type transistor 4, 14.16...
...Control MO8 type transistor, 16...Drain terminal of transistor 16, 17...Gate terminal of transistors 14 and 16, 18.19...
...N-channel MO8 type transistor, 20.21.
...P-channel MO5 type transistor. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 3
Figure 1 Figure 2 Figure 11n /

Claims (1)

【特許請求の範囲】[Claims] (1)−の導電チャネルMO8型第1トランジスタのソ
ース電極を電源の一方の端子に接続し、上記第1トラン
ジスタのゲート電極とドレイン電極を短絡し、上記第1
トランジスタの上記ドレイン電極と上記電源の他方の端
子との間に他の導電チャネルMO8型第2トランジスタ
を接続し、上記第2トランジスタのゲート電極にこれを
常時導通せしめるように直流ゲートバイアスを印加した
基準電圧発生回路と、前記両トランジスタの接続点の電
圧を一方の入力とし、他方の入力に被検出電圧を印加せ
しめる相補MO8型差動増幅回路とをそなえたことを特
徴とする電圧検出回路、(2)基準電圧発生回路および
差動増幅回路の一方あるいは両方の回路に制御入力端子
をもつMOSトランジスタを縦続封有したことを特徴と
する特許請求の範囲第1項記載の電圧検出回路。
(1) The source electrode of the conductive channel MO8 type first transistor of - is connected to one terminal of a power supply, the gate electrode and drain electrode of the first transistor are short-circuited, and the first
Another conductive channel MO8 type second transistor was connected between the drain electrode of the transistor and the other terminal of the power source, and a DC gate bias was applied to the gate electrode of the second transistor so as to make it conductive at all times. A voltage detection circuit comprising: a reference voltage generation circuit; and a complementary MO8 type differential amplifier circuit, which takes the voltage at the connection point of the two transistors as one input and applies the detected voltage to the other input. (2) The voltage detection circuit according to claim 1, wherein one or both of the reference voltage generation circuit and the differential amplifier circuit includes a cascade-sealed MOS transistor having a control input terminal.
JP17946881A 1981-11-09 1981-11-09 Voltage detecting circuit Pending JPS5880564A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17946881A JPS5880564A (en) 1981-11-09 1981-11-09 Voltage detecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17946881A JPS5880564A (en) 1981-11-09 1981-11-09 Voltage detecting circuit

Publications (1)

Publication Number Publication Date
JPS5880564A true JPS5880564A (en) 1983-05-14

Family

ID=16066371

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17946881A Pending JPS5880564A (en) 1981-11-09 1981-11-09 Voltage detecting circuit

Country Status (1)

Country Link
JP (1) JPS5880564A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1720256A2 (en) * 2005-05-02 2006-11-08 Seiko Epson Corporation Line receiver circuit
JP2008511815A (en) * 2004-07-23 2008-04-17 ビョコード イセル フランス ソシエテ アノニム Comprehensive automatic analyzer for in vivo diagnosis
US7959878B2 (en) 2006-01-25 2011-06-14 Immunodiagnostic System France Unit cuvette for analyzing a biological fluid, automatic device for in vitro analysis

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5221870A (en) * 1975-08-11 1977-02-18 Seiko Instr & Electronics Ltd Circuit for detecting battery voltage
JPS54155872A (en) * 1978-05-29 1979-12-08 Nippon Precision Circuits Power voltage detection circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5221870A (en) * 1975-08-11 1977-02-18 Seiko Instr & Electronics Ltd Circuit for detecting battery voltage
JPS54155872A (en) * 1978-05-29 1979-12-08 Nippon Precision Circuits Power voltage detection circuit

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008511815A (en) * 2004-07-23 2008-04-17 ビョコード イセル フランス ソシエテ アノニム Comprehensive automatic analyzer for in vivo diagnosis
US7943100B2 (en) 2004-07-23 2011-05-17 Immunodiagnostic System France Cuvette for in vitro diagnosis
US7998432B2 (en) 2004-07-23 2011-08-16 Immunodiagnostic System France Multidisciplinary automatic analyzer for in vitro diagnosis
JP4922931B2 (en) * 2004-07-23 2012-04-25 ビョコード イセル フランス ソシエテ アノニム Comprehensive automatic analyzer for in vivo diagnosis
EP1720256A2 (en) * 2005-05-02 2006-11-08 Seiko Epson Corporation Line receiver circuit
EP1720256A3 (en) * 2005-05-02 2007-02-21 Seiko Epson Corporation Line receiver circuit
US7408385B2 (en) 2005-05-02 2008-08-05 Seiko Epson Corporation Receiver circuit, differential signal receiver circuit, interface circuit, and electronic instrument
US7959878B2 (en) 2006-01-25 2011-06-14 Immunodiagnostic System France Unit cuvette for analyzing a biological fluid, automatic device for in vitro analysis

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