JPS5910133B2 - Power supply abnormality detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power supply abnormality detection circuit that has a small and simple configuration and detects a voltage drop in, for example, a battery power supply.

In electric watches, if the power supply voltage drops, the clock circuit or oscillation circuit will stop operating or become impaired, making it impossible to display accurate time, so it is necessary to constantly monitor the power supply voltage.

Furthermore, not only electric watches but also certain types of electronic equipment may need to detect a voltage drop in a battery power source or the like and promptly deal with a power supply abnormality. In recent years, battery-powered watches with low power consumption have been developed due to improvements in semiconductor integrated circuit technology, but a correspondingly low power consumption and compact power supply abnormality detection circuit is also required. Furthermore, electronic watches, for example, have a structure that makes it difficult to easily replace their batteries, so it is necessary to incorporate a simple power supply abnormality detection circuit into the electronic watch to constantly monitor the power status. No. The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a power supply abnormality detection circuit that can reliably detect abnormalities in a battery power source, a commercial power source, etc., has a small number of circuit components, and has low power consumption.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

In Fig. 1, terminals 1 and 2 are power supply terminals of the power supply circuit to be detected (not shown), one terminal 1 has o volts (ground potential) as a +VDD power supply, and the other terminal has -Vs.
A switching transistor (hereinafter abbreviated as pFET) 3, a variable resistance circuit 2 for adjusting the detection voltage, and N-channel field effect transistor (hereinafter abbreviated as nFET) 1
A series circuit in which four (first transistors) are connected in series is connected. In addition, nF■4 and pFE are connected in parallel with this series circuit.
An inverter circuit 6 is provided which is connected in series with T5.
of the pFET 3 and the variable resistance circuit 2. At the connection point, the input terminals of the inverter circuit I, that is, nFET4 and pFE
The point where each gate electrode is commonly connected to T5 is connected, and the output terminal of the inverter circuit, that is, each FET 4, 5 is connected.
The commonly connected drain electrodes of the transistors are connected to the gate electrode of the pFET 3 via a feedback loop T. above p
PFETl3 is connected in parallel to FET3. This PF
ETl3 and the NFETl4 constitute a sampling circuit, and the gate electrodes of these FETsl3 and l4 are connected to a signal input terminal 12 to which a sampling pulse signal with a small duty is input. In addition, 11
is a detection terminal for detecting power supply abnormality. Next, the operation in the above configuration will be explained.

A sampling pulse signal with a small duty is introduced into the signal input terminal 12 from, for example, a clock circuit, and during the high CH level of this pulse signal, the NFE
Tl4 is turned on and PFETl3 is turned off. Therefore, the input signal level to the inverter circuit is determined by the on-resistance of PFET3, the set resistance value of variable resistance circuit 2, and NFET14.
It is determined by the ratio to the sum of the on-resistances. Here, the on-resistances of PFET13 and nFET14 are set to be sufficiently smaller than the on-resistance of PFET3. On the other hand, during the period when the sampling signal is at the low (6L7) level, PFETl3 is turned on.
Since NFET14 is turned off, the power supply voltage is not detected. Therefore, it is detected whether the output voltage (-Ss) of the detected power supply circuit is "normal" or "abnormal" only during the sampling period corresponding to the small duty of the sampling pulse signal.Now, the sampling pulse signal is 6H'' If it is at the level, PFETl3 is turned off and NFETl4 is turned on as described above. Also, since the width of PFET3 increases when NFETl4 is turned on, this PFE
T3 is also turned on. Since the on-resistance of the NFET 14 is sufficiently smaller than that of the PFET, the input signal level of the inverter circuit is approximately determined by the resistance division ratio between the on-resistance of the PFET 3 and the variable resistance circuit 2. Therefore, the variable resistance circuit 2 for adjusting the detection voltage adjusts the input signal level to 'H'.
If it is set to the level, NFET4 is turned on and PFET5 is turned off, and the output signal level of the inverter circuit becomes the "L1 level", indicating a "normal" state. That is, as shown in FIG. 2b, when the output voltage level of the power supply circuit to be detected is in a normal state, the potential of the detection terminal 11 is maintained at the L'' level. When the voltage of PFET3 decreases (at this time, the sampling pulse signal is at the 6H1 level), the VGS of PFET3 decreases, the on-resistance increases, and the VDS of this PFET3 decreases.
also becomes larger. Therefore, the potential at the connection point between PFET 3 and variable resistance circuit 2 becomes 6L1 level, and the output signal level of the inverter circuit becomes H'' level, that is, +DD potential (
0 volt), this output signal level is fed back to the gate electrode of PFET 3 via feedback loop 7, and the potential of detection terminal 11 is rapidly inverted to 6H1 level. Next, when the sampling pulse signal reaches the 8L level, PFETl3 is turned on and NFETl4 is turned off, so the power supply voltage is not detected.
An abnormal signal as shown in Figure b is obtained. The detection voltage level that serves as a reference for this "abnormality" is of course adjusted by the variable resistance circuit 2. In this way, the above embodiment has a PFET l
By adding a sampling circuit consisting of FET 14 and FET 14, abnormality detection of the power supply voltage is performed intermittently, and a drop in the output voltage of the battery power supply can be monitored and detected with less current consumption.

That is, the feedback loop 7 sets the current state of the inverter circuit by performing flip-flop operation, making it possible to suppress transient current to a low level. Incidentally, the connection polarity of the power supply circuit to be detected may be reversed, and the channel type FET may also have p or n selected as appropriate.Also, any of the embodiments may be incorporated into a clock circuit constituted by a CMOS integrated circuit. When used, power supply abnormalities can be detected effectively because the number of elements is small and the circuit area is small. But of course, this invention can be applied to other things besides watches. As described in detail above, according to the present invention, it is possible to provide a novel power supply abnormality detection circuit that can detect a power supply abnormality when the power supply voltage decreases or fluctuates, and a complementary symmetrical MOS
When incorporated into an integrated circuit, the number of components is small and power consumption is low, so it is convenient for application to small electronic devices such as electronic watches.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing a power abnormality detection circuit according to an embodiment of the present invention, and FIG. 2 is an input/output waveform diagram for explaining the operation of the embodiment. 1, ``...Power terminal, 3...Switching transistor, 2...Variable resistance circuit, 14
...First transistor, Dan...Inverter circuit, 7...Feedback loop, 11...
・Detection terminal (output terminal of inverter circuit).

Claims (1)

[Claims] 1. A series circuit connected to the detected power supply circuit and consisting of a switching transistor, a resistance circuit, and a first transistor, an inverter circuit whose input signal level is determined by the voltage at the connection point of the switching transistor and the resistance circuit, and this inverter. a feedback loop wired to control conduction of the switching transistor according to an output signal level of the circuit; and a second transistor connected in parallel to the switching transistor;
The second transistors each constitute a sampling circuit that is supplied with a sampling pulse signal and whose conduction is controlled alternately, and is configured to obtain an abnormal signal from the output terminal of the inverter circuit when the output voltage of the detected power supply circuit decreases. A power supply abnormality detection circuit characterized by: