JPH0317714A - Reference voltage circuit - Google Patents
Reference voltage circuitInfo
- Publication number
- JPH0317714A JPH0317714A JP15170189A JP15170189A JPH0317714A JP H0317714 A JPH0317714 A JP H0317714A JP 15170189 A JP15170189 A JP 15170189A JP 15170189 A JP15170189 A JP 15170189A JP H0317714 A JPH0317714 A JP H0317714A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- fet
- mosfet
- series
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002347 injection Methods 0.000 abstract 1
- 239000007924 injection Substances 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
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- Control Of Electrical Variables (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野１
本発明はＭＯＳ集積回路における基準電圧回路の構成に
関する．
［発明の概要］
本発明はＭＯＳ集積回路において、エンハンスメントＭ
ＯＳＦＥＴを飽和接続し、デプリーションＭＯＳＦＥＴ
のゲートをソースと接続して成る定電流源と直列接続し
、あるいは上記エンハンスメンＩ−ＭＯＳＦＥＴの飽和
接続数を複数個直列接続したものと上記デプリーション
定電流源とを直列接続することによって、電源電圧変動
を受けにくく、しかも任意の整数倍出力が得られるよう
な基準電圧回路である。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to the configuration of a reference voltage circuit in a MOS integrated circuit. [Summary of the invention] The present invention provides enhancement M in a MOS integrated circuit.
Connect OSFET to saturation and depletion MOSFET
By connecting in series a constant current source formed by connecting the gate to the source, or by connecting in series the depletion constant current source with a plurality of saturated-connected enhancement-men I-MOSFETs in series, This is a reference voltage circuit that is not susceptible to voltage fluctuations and can obtain an output multiple of any integer.
［従来の技術１
従来より基準電圧回路はあった，その例を第３図、第４
図に示す。図中３ｌ、３４はＰチャネルＭＯＳＦＥＴ、
３２、３３はＮチャネルＭＯＳＦＥＴ、３５は出力端子
、４１は抵抗、４２は定電圧ダイオード、４３は出力端
子である。[Conventional technology 1 There have been reference voltage circuits in the past, examples of which are shown in Figures 3 and 4.
As shown in the figure. In the figure, 3l and 34 are P-channel MOSFETs,
32 and 33 are N-channel MOSFETs, 35 is an output terminal, 41 is a resistor, 42 is a constant voltage diode, and 43 is an output terminal.
第３図の例に於いては３１のＭＯＳＦＥＴと３４のＭＯ
ＳＦＥＴのゲート閾値電圧差を出力端子３５へ出力する
．
第４図の例では定電圧ダイオードの逆方向降伏電圧を出
力する．
ＩＣへの組み込みを想定すると、第３図の従来例が望ま
しい．なぜなら第４図で示した定電圧ダイオードでは逆
方向降伏電圧が十分低くできないため、動作電源電圧が
低い回路へ応用できないこと及び逆方向降伏電圧を制御
することが難かしいためである．
第３図の例ではＣＭＯＳ構成という点で良好ではあるが
、素子数が多いこと、出力電圧が固定されること、素子
の動作条件を飽和領域へ保つこと等、使用に際して配慮
すべき点がかなり多い。In the example of Figure 3, there are 31 MOSFETs and 34 MOSFETs.
The SFET gate threshold voltage difference is output to the output terminal 35. In the example shown in Figure 4, the reverse breakdown voltage of a constant voltage diode is output. Assuming integration into an IC, the conventional example shown in Figure 3 is desirable. This is because the voltage regulator diode shown in Figure 4 cannot have a sufficiently low reverse breakdown voltage, so it cannot be applied to circuits with a low operating power supply voltage, and it is difficult to control the reverse breakdown voltage. Although the example in Figure 3 has a good CMOS configuration, there are many points to consider when using it, such as the large number of elements, the fixed output voltage, and keeping the operating conditions of the elements in the saturation region. many.
従って集積化には向くが，低い電圧（特にＩＶ以下）で
動作させようとする場合，制約が大きくなり使用できな
い事がある．
［発明が解決しようとする課題］
本発明では低い電源電圧で動作し、しがち構成素子が少
なく、必要に応じて出力電圧を変化させ得るようなＭＯ
Ｓ基準電圧回路を提供することを目的としている．
〔課題を解決するための手段〕
本発明は、
（１）第１の導電形エンハンスメントＭＯＳＦＥＴと、
第１の導電形デプリーションＭＯＳＦＥＴを直列接続し
、前記第１のエンハンスメントＭＯＳＦＥＴゲート電極
を同ＦＥＴのドレイン！極へ接続し、前記第１のデプリ
ーションＭＯＳＦＥＴのゲート電極を同ＦＥＴのソース
電極と接続し、両者の直列接続点電位を出力する．
（２）前記第１の導電形エンハンスメントＭＯＳＦＥＴ
を複数個直列接続し、おのおののＦＥＴゲート電極は、
おのおののＦＥＴのドレインと接続されることにより任
意の整数倍出力を得る．ということを特徴とする．
（実 施 例１
以下具体的構成を示しながら実施例を説明する．第１図
は本発明の基本構成を示す．図中ｌは？チャネルエンハ
ンスメントＭＯ Ｓ Ｆ ＥＴ、２はＰチャネルデプリ
ーションＭＯ Ｓ Ｆ ＥＴ、３は出力端子である．
今各ＦＥＴの素子定数を次のように定める。Therefore, it is suitable for integration, but when trying to operate at a low voltage (especially below IV), restrictions become too large and it may not be possible to use it. [Problems to be Solved by the Invention] The present invention provides an MO which operates with a low power supply voltage, has a small number of constituent elements, and can change the output voltage as necessary.
The purpose is to provide an S reference voltage circuit. [Means for Solving the Problems] The present invention comprises: (1) a first conductivity type enhancement MOSFET;
First conductivity type depletion MOSFETs are connected in series, and the gate electrode of the first enhancement MOSFET is connected to the drain of the FET! The gate electrode of the first depletion MOSFET is connected to the source electrode of the first depletion MOSFET, and the potential of their series connection point is output. (2) The first conductivity type enhancement MOSFET
are connected in series, and each FET gate electrode is
By connecting to the drain of each FET, an arbitrary integer multiple output can be obtained. It is characterized by this. (Example 1) An example will be described below while showing a specific configuration. Fig. 1 shows the basic configuration of the present invention. In the figure, 1 is a channel enhancement MOSFET, and 2 is a P channel depletion MO. S FET, 3 is the output terminal. Now, the element constants of each FET are determined as follows.
β１、Ｖア■・・ ｌのＰチャネルＭＯＳＦＥＴ定数
β２ ＊ ＶＴＰ２・・・２のＰチャネルＭ Ｏ Ｓ
Ｆ Ｅ Ｔ定数
すると電源電圧Ｖｏｏ側を基準として，出力端子３へは
、
Ｖｏ ” ＶＴＰＩ ＋ ｒ丁ｚ ／ 『一．ｌ ’Ｊ
ｒ−ｘなる電圧が現れる．
ココテβ１＝Ｂｔ ． ｌ ＶＴＰ２ ｌ ＝Ｋ−Ｉ
Ｖｙｐなる設定（Ｋはイオン打込みによるシフト電圧）
を施せば
Ｖ．＝Ｋ
即ちイオン打込みによって生じるゲート閾値揉作の電圧
シフト量のみが出力されることになる。従って電源電圧
変動を持たない基４１１圧が得られる．
？２図は出力電圧を任意の整数倍とする場合の接続を示
す．図中ｌはＰチャネルエンハンスメントＭＯＳＦＥＴ
、２はＰチャネルデプリーションＭ Ｏ Ｓ Ｆ Ｅ
Ｔ、４はＮ個目のＰチャネルエンハンスメントＭＯＳＦ
ＥＴ、３は出力端子である。β1, P-channel MOSFET constant β2 of VA...l * P-channel MOSFET of VTP2...2
Using the FET constant, the voltage to the output terminal 3 is Vo ” VTPI + r dz / ``1.l' J
A voltage r-x appears. Kokote β1=Bt. l VTP2 l =K-I
Vyp setting (K is shift voltage due to ion implantation)
If you apply V. =K That is, only the voltage shift amount due to gate threshold disturbance caused by ion implantation is output. Therefore, base 411 voltage with no fluctuation in power supply voltage can be obtained. ? Figure 2 shows the connection when the output voltage is an arbitrary integer multiple. In the figure, l is a P-channel enhancement MOSFET.
, 2 is P channel depletion M O S F E
T, 4 is the Nth P-channel enhancement MOSF
ET, 3 is an output terminal.
この場合、得られる出力電圧Ｖ。は、
Ｖｏ ” （ＶＴＰ＋ ＋”７；”’：フ７丁・ｌ Ｖ
ＴＰＩ Ｉ Ｘ Ｎ＝Ｋ−Ｎ
となり、飽和接続されたＰチャネルエンハンスメントＭ
ＯＳＦＥＴの接続個数に比例した出力電圧を得る．
ここで示した具体的構成は全てＰチャネル構成であるが
、そっくりＮチャネルＭＯＳＦＥＴへ置き換えればＶ■
基準の出力電圧を同様にして得られる．
〔発明の効果］
本発明によれば、
■１ｖ以下の電圧でも動作可能．
■電源電圧依存性がない．
■簡素な回路構成である．
■出力電圧値はイオン打込み量のみで定まる。In this case, the resulting output voltage V.は、Vo」（VTP＋＋』7;」'：F7 tō・l V
TPI I
Obtain an output voltage proportional to the number of connected OSFETs. The specific configurations shown here are all P-channel configurations, but if you replace them with N-channel MOSFETs, V
The reference output voltage can be obtained in the same way. [Effects of the Invention] According to the present invention, ① Operation is possible even at a voltage of 1 V or less. ■No dependence on power supply voltage. ■It has a simple circuit configuration. ■The output voltage value is determined only by the amount of ion implantation.
■従って温度特性が小さい．
■必要に応じて任意の整数倍出力電圧を作ることち容易
である．
という利点が生じる．
本発明の応用範囲は広い。Ｍｏｓ慎ｉのため、ＮＭＯＳ
プロセス、ＣＭＯＳプロセスで製造される集積回路へ同
時集積が可能である。さらにデプリーションＭＯ Ｓ
Ｆ ＥＴの電流係数を小さく設定すれば動作ｉｉ流も減
少するため、ポータブル指向の電子回路等への利用もで
きる．応用例としては電子時計の電池寿命検出用基準電
圧源、定電圧回路用基準電圧源、温度センサ回路用基準
電圧源、ＡＤ変換用基準電圧源等が挙げられる。■Therefore, the temperature characteristics are small. ■It is easy to create any integer multiple output voltage as needed. This brings about the advantage. The scope of application of the present invention is wide. NMOS for Mos Shini
Simultaneous integration into integrated circuits manufactured by CMOS process and CMOS process is possible. Furthermore, Depletion MO S
If the current coefficient of the FET is set to a small value, the operating current will be reduced, so it can also be used in portable electronic circuits. Application examples include a reference voltage source for battery life detection in electronic watches, a reference voltage source for constant voltage circuits, a reference voltage source for temperature sensor circuits, and a reference voltage source for AD conversion.
ＭＯＳＦＥＴ ２・・・Ｐチャネルデプリーション ＭＯＳＦＥＴ ３・・・出力端子MOSFET 2...P channel depletion MOSFET 3...Output terminal
Claims (2)
第１の導電形デプリーションＭＯＳＦＥＴを直列接続し
、前記第１のエンハンスメントＭＯＳＦＥＴゲート電極
を同ＦＥＴドレイン電極へ接続し、前記第１のデプリー
ションＭＯＳＦＥＴのゲート電極を同ＦＥＴのソース電
極と接続し、両者の直列接続点電位を出力することを特
徴とする基準電圧回路。(1) a first conductivity type enhancement MOSFET;
First conductivity type depletion MOSFETs are connected in series, the gate electrode of the first enhancement MOSFET is connected to the drain electrode of the first enhancement MOSFET, the gate electrode of the first depletion MOSFET is connected to the source electrode of the FET, and both of the depletion MOSFETs are connected in series. A reference voltage circuit characterized by outputting a series connection point potential.
を複数個直列接続し、おのおののＦＥＴゲート電極は、
おのおののドレインと接続されることにより任意の整数
倍出力を得ることを特徴とする請求項１記載の基準電圧
回路。(2) The first conductivity type enhancement MOSFET
are connected in series, and each FET gate electrode is
2. The reference voltage circuit according to claim 1, wherein an arbitrary integer multiple output is obtained by connecting the respective drains.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15170189A JPH0317714A (en) | 1989-06-14 | 1989-06-14 | Reference voltage circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15170189A JPH0317714A (en) | 1989-06-14 | 1989-06-14 | Reference voltage circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0317714A true JPH0317714A (en) | 1991-01-25 |
Family
ID=15524377
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15170189A Pending JPH0317714A (en) | 1989-06-14 | 1989-06-14 | Reference voltage circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0317714A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007205902A (en) * | 2006-02-02 | 2007-08-16 | Epson Imaging Devices Corp | Light detecting circuit, electro-optical device, and electronic equipment |
-
1989
- 1989-06-14 JP JP15170189A patent/JPH0317714A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007205902A (en) * | 2006-02-02 | 2007-08-16 | Epson Imaging Devices Corp | Light detecting circuit, electro-optical device, and electronic equipment |
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