JPH0194704A - Oscillation circuit - Google Patents
Oscillation circuitInfo
- Publication number
- JPH0194704A JPH0194704A JP25300687A JP25300687A JPH0194704A JP H0194704 A JPH0194704 A JP H0194704A JP 25300687 A JP25300687 A JP 25300687A JP 25300687 A JP25300687 A JP 25300687A JP H0194704 A JPH0194704 A JP H0194704A
- Authority
- JP
- Japan
- Prior art keywords
- oscillation circuit
- voltage
- source
- inverter amplifier
- ntr
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 title claims abstract description 29
- 238000001514 detection method Methods 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 7
- 239000013078 crystal Substances 0.000 abstract description 8
- 239000003990 capacitor Substances 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract description 2
- 230000007423 decrease Effects 0.000 description 5
- 101100215778 Neurospora crassa (strain ATCC 24698 / 74-OR23-1A / CBS 708.71 / DSM 1257 / FGSC 987) ptr-1 gene Proteins 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 101100349264 Caenorhabditis elegans ntr-1 gene Proteins 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
Landscapes
- Oscillators With Electromechanical Resonators (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明′は、０Ｍ０Ｂ型水晶発振回路及び多段電圧検出
回路を有する電子時計の発振回路に関する〔従来の技術
〕
従来、０ＭＯＳ型水晶発振回路及び多段電圧検出回路を
有する電子時計の発振回路部は、第２図に示す構成にな
り【おり、第２図のインバーター増幅器のＮＴｒ、ＰＴ
ｒ のしきい値は、不変のものであった。Detailed Description of the Invention [Field of Industrial Application] The present invention' relates to an oscillation circuit for an electronic watch having a 0M0B type crystal oscillation circuit and a multi-stage voltage detection circuit. The oscillation circuit section of an electronic watch having a multi-stage voltage detection circuit has the configuration shown in Fig. 2.
The r threshold remained constant.
従来技術では、電池電圧が低下して、前記インバーター
増幅器のＮＴｒ、ＰＴｒ のしきい値電圧の和風下の
電圧になると発振が停止していた。In the prior art, oscillation stopped when the battery voltage decreased to a voltage below the threshold voltages of the NTr and PTr of the inverter amplifier.
そこで本発明は、電池電圧が大の時は、前記インバータ
ー増幅器のＮＴｒ、ＰＴｒ のしきい値電圧の和を大と
することにより、消費電流の増加を押さえ、電池電圧が
低下するに従い、前記しきい値電圧の和を下げ、発振停
止電圧を低下させ、電池寿命を延ばそうとするものであ
る。Therefore, the present invention suppresses the increase in current consumption by increasing the sum of the threshold voltages of NTr and PTr of the inverter amplifier when the battery voltage is high, and as the battery voltage decreases, This is intended to lower the sum of threshold voltages, lower the oscillation stop voltage, and extend battery life.
本発明の発振回路は、
１） α）電池を電源とし、０−Ｍ０ｉ９型インバータ
ー増幅器を有する発振回路と、前記電池電圧レベルを少
なくとも一伏態以上検出できる多段電圧検出回路を有す
る電子回路において、ｂ）前記Ｃ−ＭＯＳ型発振回路を
構成するインバーター増幅器のＮチャンネルトランジス
タ（以下ＮＴｒ と略す、）の基板電・極は前記０−
ＭＯ３型発振回路を動作させる下位側電位（以下ｙｓｓ
とする。）に、Ｐチャンネルトランジスタ（以下ｐｈｒ
と略す、）の基板電極は上位側電位（以下ＶＤＤ
とする。）に接続されており、Ｃ）前記インバーター増
幅器を構成するＮＴｒ１７）’／−スト前記Ｗａｓ
の間、及びＰＴｒ のソースと前記ＶＤＤ の間には、
前記多段電圧検出回路からの信号により抵抗値の変る抵
抗手段が接続されており、
ｄ）１！池電圧の低下に伴ない前記抵抗手段の抵抗値を
下げ、パックゲート効果により前記インバーター増幅器
の見かけ上のしきい値電圧をも下げることを特徴とする
。The oscillation circuit of the present invention includes: 1) α) An electronic circuit using a battery as a power source and having an oscillation circuit having an 0-M0i9 type inverter amplifier, and a multistage voltage detection circuit capable of detecting the battery voltage level in at least one state or more, b) The substrate electrode/pole of the N-channel transistor (hereinafter abbreviated as NTr) of the inverter amplifier constituting the C-MOS type oscillation circuit is the 0-
Lower side potential (hereinafter referred to as yss) that operates the MO3 type oscillation circuit
shall be. ), P-channel transistor (hereinafter phr)
The substrate electrode at the upper side potential (hereinafter referred to as VDD)
shall be. ), and C) the NTr 17)'/-st the Was
and between the source of PTr and the VDD,
Resistance means whose resistance value changes depending on the signal from the multistage voltage detection circuit is connected, and d) 1! The present invention is characterized in that the resistance value of the resistor means is lowered as the battery voltage decreases, and the apparent threshold voltage of the inverter amplifier is also lowered due to the pack gate effect.
本発明は以上の構成を有するので、電池電圧が大の時は
、発振回路部のインバーター増幅器のＮＴｒ、Ｘ’Ｔｒ
のしきい値電圧の和を大とし、消費電流の増加を押
さえ、電池電圧が低下するに従い、前記しきい値電圧の
和を下げ、発振停止電圧を下げる事により電池寿命を延
ばす事を可能とする〔実施例〕
以下、本発明について実施例に基づいて詳細に説明する
。Since the present invention has the above configuration, when the battery voltage is high, the NTr and X'Tr of the inverter amplifier in the oscillation circuit section are
It is possible to extend the battery life by increasing the sum of the threshold voltages to suppress the increase in current consumption, and as the battery voltage decreases, by lowering the sum of the threshold voltages and lowering the oscillation stop voltage. [Examples] Hereinafter, the present invention will be described in detail based on Examples.
第１図は、本発明の実施例を示す０−Ｍ０Ｂ型水晶発振
回路部であり、１はＰＴｒ１．ａ及び、ＮＴｒ１．ｂに
より構成されるインバーター増幅器、２．３は各々、帰
還抵抗、ドレイン抵抗＃４゜５は発振周波数調整用コン
デンサ、６は水晶振動子、Ｚ＆″！、発振出力ラインで
ある。FIG. 1 shows a 0-M0B type crystal oscillation circuit section showing an embodiment of the present invention, where 1 indicates PTr1. a and NTr1. 2.3 is a feedback resistor, drain resistor #4.5 is a capacitor for adjusting the oscillation frequency, 6 is a crystal oscillator, Z&''!, and an oscillation output line.
ＰＴｒ１．ａの基板電極は、発振回路部を動作させる上
位側電位１００（以下ＶＤＤ と略す。）に、ＮｙｒＩ
Ｉｔ）の基板電極は下位側電位１００（以下Ｖ１１８
と略す。）に接続されている。１０は前記ＰＴｒ１．
ａのソースとｖｏｏｌｏｏとの間に並列接続されたＰチ
ャンネルトランジスタ群可変抵抗手段（以下Ｒｐと略す
、）で、１０．ａ、１０゜ｂ、１０．ｃのゲート端子に
は、多段電圧検出回路からの信号ラインが接続され、１
０．ｔｌのゲートは前記Ｖａｓ２００に接続され、常に
ＯＮ状態となっている。２０は前記Ｎ？ｒ１．ｂのソー
スとｙａｓ２００との間に並列接続されたＮチャンネル
トランジスタ群可変抵抗手段（以下ＲＮと略す。PTr1. The substrate electrode of a is connected to the upper side potential 100 (hereinafter abbreviated as VDD) for operating the oscillation circuit section.
The substrate electrode of It) has a lower potential of 100 (hereinafter V118).
It is abbreviated as )It is connected to the. 10 is the PTr1.
10. P-channel transistor group variable resistance means (hereinafter abbreviated as Rp) connected in parallel between the source of a and vooloo; a, 10°b, 10. The signal line from the multi-stage voltage detection circuit is connected to the gate terminal of c.
0. The gate of tl is connected to Vas200 and is always in an ON state. 20 is the above N? r1. An N-channel transistor group variable resistance means (hereinafter abbreviated as RN) is connected in parallel between the source of yas200 and the source of yas200.
）で、２０．ａ、２０．ｂ、２０＊ｃのゲート端子には
前記多段電圧検出回路からの信号ラインが接続され、２
０．ｄのゲートは前記Ｖｆｏ１００に接続され常にＯＮ
状態となっている。), 20. a, 20. The signal line from the multi-stage voltage detection circuit is connected to the gate terminals of 20*c and 20*c.
0. The gate of d is connected to the Vfo100 and is always ON.
It is in a state.
即ち、発振開始時には、１０．ｄ、２０．（ｔによる電
圧降下分がパックゲートバイアスとして１．ａ。That is, at the start of oscillation, 10. d, 20. (The voltage drop due to t is 1.a as the pack gate bias.
ｉｂ の基板電極に印加されている。そして、電池電
圧の低下に伴ない前記多段電圧検出回路からの信号によ
り、１，０．ａ、２０．ａ → １ｏ、ｂ、２０、ｂ
→ ＩＣ１，ｃ、２０．ｃの様に順次ＯＮして行き、
つまり１０のＲｐ、２０のＲＮでの電圧降下分を減らし
、１．ａ、１．ｂ に印加されるバックゲートバイア
スを減らし、見かけ上のＬきい値電圧を下げ、発振停止
電圧を下げる事が可能となる。ib is applied to the substrate electrode. Then, as the battery voltage decreases, the signal from the multistage voltage detection circuit is detected as 1, 0, etc. a, 20. a → 1o, b, 20, b
→ IC1, c, 20. Turn them on sequentially as shown in c.
In other words, reduce the voltage drop at Rp of 10 and RN of 20, and 1. a.1. It is possible to reduce the back gate bias applied to b, lower the apparent L threshold voltage, and lower the oscillation stop voltage.
以上の実施例において、可変抵抗手段１０．２０はＰチ
ャンネルトランジスタ群、Ｎチャンネルトランジスタ群
である必要はなく、また可変段数も何段であってもよい
。In the above embodiments, the variable resistance means 10.20 need not be a P-channel transistor group or an N-channel transistor group, and the number of variable stages may be any number.
第３図に多段電圧検出回路の一例を示す。FIG. 3 shows an example of a multistage voltage detection circuit.
４０はコンパレーターで、４１０基準電圧と４６のデコ
ーダーによって切り換えられる４７．４８．４９０スイ
ツチ上の電位を比較する。つまり、一番初めは４７のス
イッチのみＯＮされており、電位が下がり、４１の基準
電圧を下回９た時点で、比較信号を出力する。この信号
が４２．４５の微分回路を通し４４．４５のカウンター
へ出力され、カウンターの内容を４６のデコーダーでデ
コードし、スイッチを４７から４８へ切ル換えると伴Ｋ
、第１図１０．２０への信号をコントロールするといっ
た様なものである。A comparator 40 compares the reference voltage 410 with the potential on the 47, 48, and 490 switches switched by the decoder 46. That is, at the beginning, only the switch 47 is turned on, and when the potential drops and falls below the reference voltage 41, a comparison signal is output. This signal passes through the differentiation circuit of 42.45 and is output to the counter of 44.45.The contents of the counter are decoded by the decoder of 46, and when the switch is changed from 47 to 48,
, 10.20 in FIG.
以上に述べた様に本発明によれば、電池電圧穴の時は、
発振インバーター増幅器の見かけ上のしきい値の和を大
として消費電流を押さえ、電池電圧の低下に従い、前記
しきい値の和を下げる事により、発振停止電圧を下げ、
電池寿命を延ばす事を可能とした。As described above, according to the present invention, when the battery voltage hole is
The sum of the apparent thresholds of the oscillation inverter amplifier is increased to suppress current consumption, and as the battery voltage decreases, the sum of the thresholds is lowered to lower the oscillation stop voltage.
This made it possible to extend battery life.
第１図は、本発明に係るｑ−ＭＯＥＪ型水晶発振回路図
、第２図は従来の発振回路図。
第３図は多段電圧検出回路の一例を示す図である。
１・・・・・・・・・０−ＭＯＳインバーター６・・・
・・・・・・水晶振動子
１０・・・・・・・・・Ｐチャンネルトランジスタ可変
抵抗手段
２０・・・・・・・・・Ｎチャンネルトランジスタ可変
抵抗手段
以上FIG. 1 is a q-MOEJ type crystal oscillation circuit diagram according to the present invention, and FIG. 2 is a conventional oscillation circuit diagram. FIG. 3 is a diagram showing an example of a multistage voltage detection circuit. 1...0-MOS inverter 6...
......Crystal resonator 10...P-channel transistor variable resistance means 20...N-channel transistor variable resistance means and above
Claims (3)
増幅器を有する発振回路と、前記電池電圧レベルを少な
くとも一状態以上検出できる多段電圧検出回路を有する
電子回路において、 ｂ）前記Ｃ−ＭＯＳ型発振回路を構成するインバーター
増幅器のＮチャンネルトランジスタ（以下ＮＴｒと略す
。）の基板電極は前記Ｃ−ＭＯＳ型発振回路を動作させ
る下位側電位（以下Ｖ＿Ｓ＿Ｓとする。）に、Ｐチャン
ネルトランジスタ（以下ＰＴｒと略す。）の基板電極は
上位側電位（以下Ｖ＿Ｄ＿Ｄとする。）に接続されてお
り、 ｃ）前記インバーター増幅器を構成するＮＴｒのソース
と前記Ｖ＿Ｓ＿Ｓの間には、前記多段電圧検出回路から
の信号により抵抗値の変る抵抗手段が接続されている事
を特徴とする発振回路。(1) a) An electronic circuit using a battery as a power source and having an oscillation circuit having a C-MOS type inverter amplifier and a multi-stage voltage detection circuit capable of detecting at least one state or more of the battery voltage level, b) the C-MOS type The substrate electrode of the N-channel transistor (hereinafter referred to as NTr) of the inverter amplifier constituting the oscillation circuit is connected to the lower side potential (hereinafter referred to as V_S_S) for operating the C-MOS type oscillation circuit, and the substrate electrode of the P-channel transistor (hereinafter referred to as PTr) ) is connected to the upper side potential (hereinafter referred to as V_D_D); c) between the source of the NTr constituting the inverter amplifier and the V_S_S, there is a An oscillation circuit characterized by being connected to a resistance means whose resistance value changes depending on a signal.
スと前記Ｖ＿Ｄ＿Ｄの間には、前記多段電圧検出回路か
らの信号により抵抗値の変る抵抗手段が接続されている
事を特徴とする特許請求の範囲第１項記載の発振回路。(2) A resistor whose resistance value changes depending on a signal from the multi-stage voltage detection circuit is connected between the source of the PTr constituting the inverter amplifier and the V_D_D. The oscillation circuit described in item 1.
スと前記Ｖ＿Ｓ＿Ｓの間、及びＰＴｒのソースと前記Ｖ
＿Ｄ＿Ｄの間には、前記多段電圧検出回路からの信号に
より抵抗値の変る抵抗手段が接続されている事を特徴と
する特許請求の範囲第１項記載の発振回路。(3) between the source of the NTr constituting the inverter amplifier and the V_S_S, and between the source of the PTr and the V_S_S;
2. The oscillation circuit according to claim 1, further comprising a resistor whose resistance value changes depending on a signal from the multi-stage voltage detection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25300687A JPH0194704A (en) | 1987-10-07 | 1987-10-07 | Oscillation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25300687A JPH0194704A (en) | 1987-10-07 | 1987-10-07 | Oscillation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0194704A true JPH0194704A (en) | 1989-04-13 |
Family
ID=17245178
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25300687A Pending JPH0194704A (en) | 1987-10-07 | 1987-10-07 | Oscillation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0194704A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2711285A1 (en) * | 1993-10-15 | 1995-04-21 | Hewlett Packard Co | Method and device for controlling the pulse rate of an oscillator |
| WO1999026334A1 (en) * | 1997-11-14 | 1999-05-27 | Seiko Epson Corporation | Low-voltage oscillation amplifier circuit and portable electronic device comprising the same |
| US6097257A (en) * | 1997-01-22 | 2000-08-01 | Seiko Epson Corporation | Crystal oscillator circuit having transistor with back gate voltage control |
| US8939112B2 (en) | 2009-10-22 | 2015-01-27 | Ihi Corporation | Buckstay connecting system |
-
1987
- 1987-10-07 JP JP25300687A patent/JPH0194704A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2711285A1 (en) * | 1993-10-15 | 1995-04-21 | Hewlett Packard Co | Method and device for controlling the pulse rate of an oscillator |
| US5481228A (en) * | 1993-10-15 | 1996-01-02 | Hewlett-Packard Corporation | Method and apparatus for controlling oscillator duty cycle |
| US6097257A (en) * | 1997-01-22 | 2000-08-01 | Seiko Epson Corporation | Crystal oscillator circuit having transistor with back gate voltage control |
| WO1999026334A1 (en) * | 1997-11-14 | 1999-05-27 | Seiko Epson Corporation | Low-voltage oscillation amplifier circuit and portable electronic device comprising the same |
| US6229405B1 (en) | 1997-11-14 | 2001-05-08 | Seiko Epson Corporation | Low-voltage oscillation amplifying circuit |
| US8939112B2 (en) | 2009-10-22 | 2015-01-27 | Ihi Corporation | Buckstay connecting system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5485126A (en) | Ring oscillator circuit having output with fifty percent duty cycle | |
| EP0497319B1 (en) | Semiconductor integrated circuit device having substrate potential detection circuit | |
| US6696858B2 (en) | Level-shifting circuit | |
| US3959744A (en) | CMOS oscillator having bias circuit outside oscillator feedback loop | |
| US5325074A (en) | Oscillator with supply voltage changeover according to activated and disabled states of a microcomputer | |
| JP3201339B2 (en) | Oscillation circuit | |
| JPH0194704A (en) | Oscillation circuit | |
| JPH0254698B2 (en) | ||
| US4032864A (en) | Electronic circuit having a misfet as an amplifying element | |
| JP3638696B2 (en) | VCO circuit driving method and VCO circuit | |
| KR20030072527A (en) | Generator of dc-dc converter | |
| US4001721A (en) | Field effect transistor miller integrator oscillator with temperature compensating impedance | |
| US4746810A (en) | Pulse generating circuit | |
| JPH01101008A (en) | Crystal oscillation circuit | |
| JP3132212B2 (en) | Crystal oscillation circuit | |
| JP3255581B2 (en) | Oscillator circuit | |
| JPS58196464A (en) | Voltage drop detection circuit | |
| JPS5880564A (en) | Voltage detecting circuit | |
| JPS6036644B2 (en) | oscillation circuit | |
| JPH04135302A (en) | Cmos inverter oscillation circuit | |
| JP2861021B2 (en) | CMOS crystal oscillation circuit | |
| JPH0645830A (en) | Oscillation circuit | |
| JPH05315941A (en) | Logic circuit | |
| JPS6034847B2 (en) | crystal oscillation circuit | |
| JPH0548334A (en) | Cmos oscillation circuit |