JP2861021B2 - CMOS crystal oscillation circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a CMOS crystal oscillation circuit configured by a CMOS inverter circuit.

[Prior Art] A circuit shown in FIG. 4 is conventionally known as a crystal oscillation circuit using a CMOS inverter circuit. This circuit is
A complementary pair of a P-channel MOS transistor 1 and an N-channel MOS transistor 2 constituting a CMOS inverter circuit is connected between a power supply _VDD and a ground GND, and a feedback resistor 3 and a crystal oscillator are connected between the input and output of the CMOS inverter circuit. The external oscillators 5 and 6 are connected between both ends of the crystal unit 4 and the ground, respectively.

In this CMOS crystal oscillation circuit, a CMOS
Stable oscillation is maintained by setting an appropriate DC bias point on the input side of the inverter.

[Problems to be Solved by the Invention] The current consumption of the above-mentioned conventional CMOS crystal oscillation circuit is determined by the P-channel MOS transistor 1 and the N-channel MOS transistor.
This is a through current flowing through the CMOS inverter circuit composed of the transistor 2 and this through current shows a strong positive dependency on the power supply voltage of the inverter circuit. That is, the through current increases at a high power supply voltage. This characteristic has a great effect not only on the increase in current consumption at high power supply voltage but also on the frequency stability. Since a CMOS crystal oscillation circuit is used to generate a reference clock such as a clock or a computer, a decrease in frequency stability causes a decrease in performance of a device using the circuit.

Therefore, as shown in FIG. 5, between the P-channel MOS transistor 1 constituting the CMOS inverter circuit and the power supply V _DD ,
Also, a circuit has been proposed in which current-limiting resistors 7 and 8 are inserted between the N-channel MOS transistor 2 and the ground GND to solve the problem of increased current consumption and reduced frequency stability at high power supply voltage. .

However, since the through current flowing through the CMOS inverter circuit is inversely proportional to the oscillation start voltage and the oscillation sustaining voltage, limiting the through current in this way at a low power supply voltage causes the oscillation starting voltage and the oscillation sustaining voltage. Is high.

As described above, the conventional CMOS crystal oscillation circuit has a problem that it is not possible to satisfy both the oscillation start voltage, the oscillation sustain voltage, and the power consumption.

The present invention has been made in view of the above problems, and has as its object to provide a CMOS crystal oscillation circuit that can maintain both oscillation start voltage, oscillation sustain voltage, and power consumption at preferable values. .

[Means for Solving the Problems] A CMOS crystal oscillation circuit according to a first invention includes a CMOS inverter circuit, a crystal resonator and a feedback resistor connected to a feedback path of the CMOS inverter circuit, and the CMOS inverter circuit. A first switch connected between a P-channel MOS transistor to be constituted and a first power supply;
A second switch and a first resistor connected in series between the MOS transistor and the first power supply, and a second switch and a first power supply connected between the N-channel MOS transistor forming the CMOS inverter circuit and the second power supply; A third switch, a fourth switch and a second resistor connected in series between the N-channel MOS transistor and a second power supply, and detecting a power supply voltage of the first and second power supplies. When the power supply voltage is lower than a predetermined value, the first and third switches are turned on, and the second and fourth switches are turned off, and the power supply voltage is higher than a predetermined value. In this case, the second and fourth switches are turned on, and the first and third switches are turned on.
A voltage determining circuit for turning off the switch, the voltage determining circuit comprising: a CR delay circuit and an inverter delay circuit that receive an output of the CMOS inverter circuit; and a clock input terminal that outputs the output of the CR delay circuit. And a D-type flip-flop circuit for inputting an output of the inverter delay circuit to a data input terminal and controlling each of the switches by a normal output and an inverted output.

Further, the CMOS crystal oscillation circuit according to the second invention has a first
A CMOS inverter circuit, a second CMOS inverter circuit connected in parallel with the first CMOS inverter circuit and having an on-resistance larger than that of the first CMOS inverter circuit, and feedbacks of the first and second CMOS inverter circuits. A crystal oscillator and a feedback resistor connected to a path, a first switch connected between the first CMOS inverter circuit and a power supply,
A second switch connected between the second CMOS inverter circuit and a power supply; and a power supply voltage of the power supply, and when the power supply voltage is smaller than a predetermined value, the first switch is turned off. A voltage determination circuit that turns on the second switch, turns off the second switch, and turns on the second switch and turns off the first switch when the power supply voltage is larger than a predetermined value; Wherein the voltage determination circuit includes a CR having an output of the CMOS inverter circuit as an input.
A delay circuit, an inverter delay circuit, and an output of the CR delay circuit are input to a clock input terminal, and an output of the inverter delay circuit is input to a data input terminal, and each switch is controlled by a normal output and an inverted output. And a flip-flop circuit.

[Operation] In the first invention, when the power supply voltage is smaller than a predetermined value, the voltage determination circuit turns on the first and third switches and turns off the second and fourth switches, so that the CMOS inverter Since the circuit is directly connected to the first and second power supplies, a decrease in the through current is suppressed, and the oscillation start voltage and the oscillation sustain voltage can be suppressed to low values. When the power supply voltage is higher than the predetermined value, the voltage judgment circuit turns off the first and third switches and turns on the second and fourth switches. The second power supply is connected to the first and second power supplies via the second resistor, the through current is suppressed, and low power consumption can be achieved.

In the second invention, when the power supply voltage is smaller than a predetermined value, the power supply determination circuit turns on the first switch and turns off the second switch, so that the first CMOS inverter circuit is connected to the power supply. Connected. Since the ON resistance of the first CMOS inverter circuit is smaller than that of the second CMOS inverter circuit, a decrease in the through current is suppressed, and the oscillation start voltage and the oscillation sustain voltage can be suppressed to low values. When the power supply voltage is higher than a predetermined value, the power supply determination circuit turns off the first switch and turns on the second switch, so that the second on-resistance is larger than that of the first CMOS inverter circuit. A CMOS inverter circuit is connected to the power supply. For this reason, through current is suppressed, and low power consumption can be achieved.

When the voltage determination circuit includes a CR delay circuit and an inverter delay circuit for inputting the output of the CMOS inverter circuit, and a D-type flip-flop circuit for using these delay outputs as a clock input and a data input, respectively, the CR Since the delay circuit is not affected by the fluctuation of the power supply voltage, and the inverter delay circuit is affected by the fluctuation of the power supply voltage, the output timing of both delay circuits changes according to the level of the power supply voltage. Therefore, a change in the power supply voltage can be detected by detecting this timing change by a D-type flip-flop circuit to which these outputs are input.

Embodiment An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing a configuration of a CMOS crystal oscillation circuit according to a first embodiment of the present invention. In FIG. 1, the same components as those in FIGS. 4 and 5 are denoted by the same reference numerals. Therefore, the description of the overlapping part will be omitted.

The circuit of this embodiment includes a P-channel MOS transistor 11 serving as a first switch between a source of a P-channel MOS transistor 1 constituting a CMOS inverter circuit and a power supply _VDD.
Is connected, and a second
Is connected to a series circuit of a P-channel MOS transistor 12 and a resistor 7 serving as a switch. Also,
This circuit is an N-channel MO that constitutes a CMOS inverter circuit.
An N-channel MOS transistor 13 serving as a third switch is connected between the source of the S transistor 2 and the ground GND, and an N-channel MOS transistor 14 serving as a fourth switch and a resistor 8 are connected in parallel with the transistor 13. A series circuit is connected.

The output V _O of the CMOS inverter circuit is input to the voltage determination circuit 15. The voltage determining circuit 15 has two delay circuits at its input. The first delay circuit is a CR delay circuit that is not affected by fluctuations in the power supply voltage, and is composed of an integrating circuit including a resistor 21 and a capacitor 22, and an inverter 23 that shapes the output waveform of the integrating circuit.
The second delay circuit is an inverter delay circuit that is affected by fluctuations in power supply voltage, and is configured by continuously connecting inverters 24, 25, and 26. Of these two delay circuits, the output of the CR delay circuit is input to the clock input terminal of the D-type flip-flop circuit 27. The output of the inverter delay circuit is input to the data input terminal of the D-type flip-flop circuit 27. The Q output of the D-type flip-flop circuit 27 is input to each gate of the transistors 11 and 14, and the output is input to each gate of the transistors 12 and 13.

According to this configuration, the CR that is not affected by the power supply voltage fluctuation
By setting the delay value of the delay circuit and the delay circuit affected by the power supply voltage to an appropriate value, when the power supply voltage is low, as shown on the left side of FIG. Since the delay value of the inverter delay circuit increases, the D-type flip-flop circuit 27
The Q output is “L” and the output is “H”.
1 and 13 are turned on, and transistors 12 and 14 are turned off. Therefore, the P-channel MO constituting the inverter of the crystal oscillation circuit
The sources of the S transistor 1 and the N-channel MOS transistor 2 are directly connected to the power supply _VDD and the ground GND, respectively.

On the other hand, when the power supply voltage is high, the delay value of the inverter circuit becomes smaller than the delay value of the CR delay circuit as shown on the right side of FIG. The output becomes “L”, the transistors 11 and 13 are turned off, and the transistors 12 and 14 are turned on. For this reason, P which constitutes the inverter of the crystal oscillation circuit
Power source limiting resistors 7 and 8 are connected to the respective sources of the channel MOS transistor 1 and the N-channel MOS transistor 2.

As described above, according to the configuration of the CMOS crystal oscillation circuit shown in FIG. 1, the through current of the inverter circuit is limited by the resistors 7 and 8 at a high power supply voltage, and the resistance is low at a low power supply voltage.
The oscillation start voltage and the oscillation sustaining voltage can be suppressed to low values because the voltage does not pass through 7, 8.

FIG. 3 is a diagram showing a configuration of a CMOS crystal oscillation circuit according to a second embodiment of the present invention.

In the first embodiment described with reference to FIG.
And the transistor switch to select whether to connect or disconnect the current limiting resistor to the inverter circuit.
In the second embodiment, two inverter circuits having different on-resistances are switched by the voltage determination circuit 15.

That is, in FIG. 3, a P-channel MOS transistor 31 and an N-channel M
The OS transistor 32 has a larger dimension (smaller on-resistance) than the P-channel MOS transistor 33 and the N-channel MOS transistor 34 constituting the second CMOS inverter circuit. Further, a P-channel MOS transistor as a switch is provided between the source of the P-channel MOS transistor 31 constituting the first CMOS inverter circuit and the power supply _VDD.
An OS transistor 35 is connected, and a P-channel MOS transistor 36 as a switch is connected between the source of the N-channel MOS transistor 33 constituting the second CMOS inverter circuit and the power supply _VDD .

With such a configuration, when the power supply voltage is low,
The transistor 35 is turned on and the transistor 36 is turned off by the voltage determination circuit 15, and the P-channel MOS transistor 31 is selected as the N-channel MOS transistor 32. Also,
When the power supply voltage increases, the transistor 35 is turned off, the transistor 36 is turned on, and the P-channel MOS transistor 33 is turned on.
And N-channel MOS transistor 34 are selected. Therefore, when the high power supply voltage is used, the crystal oscillation circuit is configured by the second inverter circuit having a small dimension. Therefore, the current consumption is small. When the power supply voltage is low, the crystal oscillation circuit is configured by the first inverter circuit having the large dimension. , The oscillation start voltage and the oscillation maintenance voltage are lowered.

[Effects of the Invention] As described above, according to the present invention, the elements constituting the oscillation circuit are switched by the voltage determination circuit for determining the level of the power supply voltage. It is possible to provide a CMOS crystal oscillation circuit with improved frequency stability and low oscillation voltage and low oscillation sustain voltage at low power supply voltage.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a CMOS crystal oscillation circuit according to a first embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the circuit, and FIG. 3 is a second embodiment of the present invention. And FIGS. 4 and 5 are circuit diagrams respectively showing a conventional CMOS crystal oscillation circuit. 1,11,12,31,33,35,36; P-channel MOS transistor, 2,1
3, 14, 32, 34; N-channel MOS transistor, 3; feedback resistor,
4; crystal oscillator, 5, 6; external capacitor, 7, 8, 21; resistor, 1
5; voltage determination circuit, 22; capacitor, 23 to 26; inverter, 27; D-type flip-flop circuit

Claims (2)

(57) [Claims] 1. A CMOS inverter circuit, a crystal unit and a feedback resistor connected to a feedback path of the CMOS inverter circuit, and a P-channel MOS constituting the CMOS inverter circuit.
A first switch connected between a transistor and a first power supply; a second switch and a first resistor connected in series between the P-channel MOS transistor and a first power supply; N-channel for CMOS inverter circuit
A third transistor connected between the MOS transistor and the second power supply;
Switch, the N-channel MOS transistor and the second
And a fourth switch and a second resistor connected in series between the power supply and a power supply voltage of the first and second power supplies. If the power supply voltage is smaller than a predetermined value, The first and third switches are turned on, and the second and fourth switches are turned on.
A voltage determination circuit for turning off the first switch, turning off the second and fourth switches when the power supply voltage is larger than a predetermined value, and turning off the first and third switches. Wherein the voltage determination circuit comprises:
A CR delay circuit and an inverter delay circuit that receive an output of the CMOS inverter circuit as inputs, an output of the CR delay circuit is input to a clock input terminal, and an output of the inverter delay circuit is input to a data input terminal; A CMOS crystal oscillation circuit comprising: a D-type flip-flop circuit that controls each of the switches with an inverted output. 2. A first CMOS inverter circuit, comprising:
A second CMOS inverter circuit connected in parallel with the CMOS inverter circuit and having a higher on-resistance than the first CMOS inverter circuit, a crystal oscillator connected to the feedback paths of the first and second CMOS inverter circuits, A feedback resistor, a first switch connected between the first CMOS inverter circuit and the power supply, a second switch connected between the second CMOS inverter circuit and the power supply, And if the power supply voltage is smaller than a predetermined value, the first switch is turned on and the second switch is turned off, and the power supply voltage is larger than a predetermined value. A voltage decision circuit for turning on the second switch and turning off the first switch, wherein the voltage decision circuit has a CR delay having an output of the CMOS inverter circuit as an input. Circuit and an inverter delay circuit, and a D-type circuit for inputting the output of the CR delay circuit to a clock input terminal, inputting the output of the inverter delay circuit to a data input terminal, and controlling each of the switches by a normal output and an inverted output. A CMOS crystal oscillation circuit comprising a flip-flop circuit.