JPH07336216A - Voltage controlled oscillator - Google Patents

Abstract

PURPOSE:To extend the linear region of a VCO whose oscillating frequency changes in proportion to an input voltage. CONSTITUTION:Two bias voltage generating sections 51, 52 have a different output voltage characteristic from each other with respect to an input voltage Vi and provide the output voltage based on the input voltage Vi to transfer gates 53, 54 respectively. The transfer gates 53, 54 are complementarily set on/off with outputs of inverters 55, 56 depending on the level of the input voltage Vi to select an output voltage from bias voltage generating sections 51, 52 and to give the selected voltage to gates of PMOS 61c-65c. On the other hand, the input voltage Vi is given to gates of NMOS 61d-54d. A delay time being the output of inverters 61-54 is controlled by the change in the conduction state of the PMOS 61c-65c and the NMOS 61d-65d and the oscillated frequency of a ring oscillator is linearly changed with respect to the input voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a PLL (Phase Locked).
The present invention relates to a voltage controlled oscillator (hereinafter, referred to as VCO) which is used in a loop (hereinafter, referred to as PLL) or the like and is configured by a semiconductor integrated circuit and outputs an oscillation frequency according to an input voltage.

[0002]

2. Description of the Related Art First Conventional Example FIG. 2 is a circuit diagram of a VCO showing a first conventional example. This VCO is composed of a semiconductor integrated circuit, and a bias voltage generation circuit 1 for generating a bias voltage for an input voltage Vi.
0, the ring oscillator 20, and the output inverter 30
And are equipped with. The bias voltage circuit 10 includes a P-type channel field effect transistor (hereinafter referred to as PMOS) 11 and an N connected between a power supply potential Vdd and a ground potential Vss.
It has a type channel field effect transistor (hereinafter referred to as NMOS) 12. The source of the PMOS 11 is connected to the power supply potential Vdd, and the drain of the PMOS 11 is connected to the drain of the NMOS 12 at the node N10. P
In the MOS 11, the voltage of the node N10 is input to the gate, and the voltage of the node N10 controls the voltage conduction state of the PMOS 11. The source of the NMOS 12 is connected to the ground potential Vss, and the input voltage Vi is input to the gate of the NMOS 12.

The ring oscillator 20 outputs the oscillation frequency based on the input signal Vi to the output inverter 30, and the output of the output inverter 30 is the output terminal Ou.
It is output from t. The ring oscillator 20 has a power supply potential V
It has five stages of inverters 21, 22, 23, 24, 25 provided between dd and the ground potential Vss. Each of the inverters 21 to 25 is composed of CMOS. That is, the inverter 21 is composed of a PMOS 21a and an NMOS 21b whose drains are connected to each other at a node N21. Similarly, each inverter 22, 23, 24, 25
A PMOS 22a and an NMOS 22b whose drains are connected to nodes N22, N23, N24 and N25, and a PM
OS 23a, NMOS 23b, and PMOS 24a, NM
It is composed of an OS 24b, a PMOS 25a, and an NMOS 25b. Each node N21, N22, N2
3, N24 are connected to the gates of the CMOS of the next stage as the output terminals of the inverters 21, 22, 23 and 24, and the node N25 is connected to the output terminal of the output inverter 30 and the CMOS of the inverter 21. Are connected to the gates of the PMOS 21a and the NMOS 21b. 21, 22, 23, 24, 25 of each inverter
Sources of the PMOSs 21a to 25a and the power supply potential Vdd
Between them are connected PMOSs 21c to 25c for controlling currents flowing in the PMOSs 21a to 25a, respectively, and sources of the NMOSs 21b to 25b and the ground potential Vs.
Between s, the NMOSs 21d to 25d for controlling the currents flowing in the NMOSs 21b to 25b are connected, respectively. A node N10 which is an output terminal of the bias generation circuit 10 is connected to the gates of the PMOSs 21c to 25c,
The PMOSs 21c to 25c have a configuration in which the conduction state is controlled by the voltage of the node N10. NMOS 21d-25d
An input voltage Vi is input to the gate of, and the conduction state of the NMOSs 21d to 25d is controlled by the input voltage Vi.

FIG. 3 is a characteristic diagram showing the output voltage with respect to the input voltage of the bias voltage generating circuit of FIG. 2, and the operation of the VCO of FIG. 2 will be described with reference to this diagram. Input voltage Vi
Is applied to the gate of the NMOS 12 and its input voltage Vi
The resistance value of the NMOS 12 changes according to the
The voltage of 0 changes. As the voltage of the node N10 changes,
The conduction state of the PMOS 11 also changes and the voltage of the node N10 is fixed. Therefore, the voltage of the node N10, which is the output terminal of the bias voltage generating circuit, drops as the input voltage Vi increases as shown in FIG. On the other hand, ring oscillator 2
0, the inverter 21 inputs the voltage of the node N25, the other inverters 22 to 25 input the voltages of the nodes N21 to N24 of the preceding inverters, and the inverters 21 to 25 invert from the output terminals of the nodes N21 to 25. Output voltage. That is, the voltage of the node N25 oscillates. Here, for example, the output voltage of the node N21 in the inverter 21 is delayed and delayed by the next-stage inverter 22.
Be transmitted to. The delay time in this delay depends on the gate capacitance of the PMOS 22a and the NMOS 22b of the inverter 22 and the current flowing through the PMOS 21a, 21c and the NMOS 21b, 21d in the inverter 21. Similarly, each of the inverters 22 to 25 delays the output voltage corresponding to the input voltage and sends it to the next stage. Each PMO
Voltages from the node N10 of the bias generation circuit 10 are input to the gates of S21c to 25c, and the gates of the PMOSs 21c to 25c.
The resistance value of 25c is changed to control the conduction state. That is, the current from the power supply voltage Vdd to the PMOSs 21a to 25a is controlled. Similarly, the NMOSs 21d to 25
The conduction state of d is controlled by the input voltage Vi, and NM
The current with respect to the ground potential Vss of the OS 21b to 25b is controlled. As a result, the delay time in each of the inverters 21 to 25 is controlled and the oscillation frequency f is controlled. Figure 4
FIG. 4 is a characteristic diagram showing a relationship between an input voltage of the VCO of FIG. 2 and an oscillation frequency. The voltage of the node N25 is inverted by the output inverter 30 and output from the output terminal Out. That is, for example, when the input voltage Vi increases, the oscillation frequency f increases and is output as shown in FIG.

Second Conventional Example FIG. 5 is a circuit diagram of a VCO showing a second conventional example. This VCO has a bias voltage generating circuit 40 different from that of the first embodiment, which generates a bias voltage in response to an input voltage Vi from an input terminal, and a ring oscillator 20 as in FIG.
And an output inverter 30. The bias voltage circuit 40 has a PMOS 41 and an NMOS 42 connected between the power supply potential Vdd and the ground potential Vss.
The source of the PMOS 41 is connected to the power supply potential Vdd, and P
The drain of the MOS 41 is connected to the drain of the NMOS 42 at the node N40. The input voltage Vi is input to the gate of the PMOS 41, and the gate of the NMOS 42 is connected to the node N40. The voltage of the node N40 controls the conduction state of the NMOS 42. N
The source of the MOS 42 is connected to the ground potential Vss. The ring oscillator 20 outputs the oscillation frequency f based on the input signal Vi to the output inverter 30, and the output voltage of the ring oscillator 20 is output from the output terminal Out via the output inverter 30. The ring oscillator 20 has the same configuration as that of FIG. 2, and includes five stages of inverters 21, 22, 23, 24, 25, and PMOSs 21c to 25d for controlling delay times in the respective inverters 21, 22, 23, 24, 25. NMOS 21
d to 25d. A node N40 in the bias generation circuit 40 is connected to the gates of the PMOSs 21c to 25c, and the PMOSs 21c to 25c have a configuration in which the conduction state is controlled by the voltage of the node N40. NMOS 21d
The input voltage Vi is input to the gates of .about.25d, and the conduction state of the NMOSs 21d to 25d is controlled by the input voltage Vi.

FIG. 6 is a characteristic diagram showing the output voltage with respect to the input voltage of the bias voltage generating circuit of FIG. 5, and the operation of the VCO of FIG. 5 will be described with reference to this figure. Input voltage Vi
Is applied to the gate of the PMOS 41, and its input voltage Vi
The resistance value of the PMOS 41 changes according to
The voltage of 0 changes. As the voltage of the node N40 changes,
The conduction state of the NMOS 42 also changes and the voltage of the node N40 is fixed. Therefore, the voltage of the node N40, which is the output terminal of the bias voltage generation circuit 40, drops when the input voltage Vi increases as shown in FIG. On the other hand, in the ring oscillator 20, the inverter 21 inputs the voltage of the node N25, the other inverters 22 to 25 input the voltages of the nodes N21 to N24 of the preceding-stage inverters, and the inverters 21 to 25 output the node N21. ~ 2
Inverted voltage is output from 5. Therefore, the voltage of the node N25 oscillates. Each of the inverters 21 to 25 delays the output voltage corresponding to the input voltage and sends it to the next stage. The voltage from the node N40 of the bias generation circuit 40 is input to the gates of the PMOSs 21c to 25c, and PM
The resistance values of the OSs 21c to 25c change to control the conduction state. That is, the current from the power supply voltage Vdd to the PMOSs 21a to 25a is controlled. Similarly, NMOS2
The conduction states of 1d to 25d are controlled by the input voltage Vi, and the currents of the NMOSs 21b to 25b with respect to the ground potential Vss are controlled. As a result, each inverter 21-2
The delay time in 5 is controlled to control the oscillation frequency f. FIG. 7 is a characteristic diagram showing the relationship between the input voltage of the VCO of FIG. 5 and the oscillation frequency. The voltage of the node N25 is inverted by the output inverter 30 and output from the output terminal Out. That is, for example, when the input voltage Vi increases, the oscillation frequency f increases and is output as shown in FIG.

[0007]

However, the conventional VCO has the following problems. When used in a PLL or the like, since it is necessary to output the oscillation frequency f corresponding to the input voltage Vi, a VCO in which the oscillation frequency f changes linearly with respect to the change in the input voltage Vi is required. A VCO having a wide linear range in voltage characteristics is required. Therefore, the bias voltage generating circuit needs to generate an output voltage having linearity that is inversely proportional to the input voltage. For example, in the first conventional example using the bias generation circuit 20 of FIG. 2, as shown in FIG.
Becomes close to the power supply voltage Vdd, the bias voltage generation circuit 2
0 cannot generate an output voltage having a linearity inversely proportional to the input voltage Vi. Therefore, the oscillation frequency f of the VCO cannot maintain the linearity as shown in FIG. On the other hand, in the second conventional example using the bias generation circuit 40 of FIG. 5, the input voltage Vi is the ground potential Vs as shown in FIG.
When approaching s, the bias voltage generation circuit 40 receives the input voltage V
An output voltage having a linearity inversely proportional to i cannot be generated, and the VCO oscillation frequency f cannot maintain a linearity as shown in FIG. That is, the conventional VCO has a problem that the range in which the input voltage characteristic of the oscillation frequency f is linear is narrow.

[0008]

In order to solve the above-mentioned problems, the present invention provides a bias voltage generating circuit for generating a bias voltage corresponding to an input voltage, and an output of each stage inverter in a built-in odd number stage inverter. The voltage is delayed and supplied to each of the next-stage inverters, the output voltage of the final-stage inverter is delayed and supplied to the first-stage inverter, and oscillates. Based on the input voltage and the bias voltage, the inverter of each stage is delayed. In the voltage controlled oscillator that outputs the frequency corresponding to the input voltage, the bias voltage generating circuit is configured as follows. That is, the bias voltage generation circuit has a plurality of bias voltage generation units having different output voltage characteristics with respect to the input voltage, and generates a voltage generated by the plurality of bias voltage generation units according to the input voltage. The bias voltage is selected.

[0009]

According to the present invention, since the VCO is configured as described above, the plurality of bias voltage generating sections in the bias voltage generating circuit have different output voltage characteristics with respect to the input voltage, and the bias voltage generating circuit. Selects the output of the bias voltage generator as the bias voltage according to the input voltage. The bias voltage and the input voltage control the delay of the output voltage of the odd-numbered inverters in the ring oscillator, and the ring oscillator oscillates at the frequency corresponding to the input voltage. Therefore, the above problem can be solved.

[0010]

1 is a circuit diagram of a VCO showing an embodiment of the present invention. The VCO is composed of a semiconductor integrated circuit and includes a bias voltage generating circuit 50 that generates a bias voltage based on an input voltage Vi from an input terminal In, a ring oscillator 60, and an output inverter 70.
The bias voltage generation circuit 50 includes bias voltage generation units 51 and 52 having the same configurations as the bias voltage generation circuits 20 and 40 of the first and second conventional examples, respectively. As shown in FIGS. 3 and 6, the bias voltage generators 51 and 52 have different output voltage characteristics with respect to the input voltage Vi. The bias voltage generator 51 includes a PMOS connected between the power supply potential Vdd and the ground potential Vss.
It has 51a and NMOS 51b. PMOS 5
The source of 1a is connected to the power supply potential Vdd, and the PMOS 5
The drain of 1a is connected to the drain of NMOS 51b at node N51. Node N5 in PMOS 51a
The voltage of 1 is input to the gate which is the control electrode,
The voltage of 51 controls the conduction state of the PMOS 51a. The source of the NMOS 51a is connected to the ground potential Vss, and the gate of the NMOS 51b has an input voltage Vi.
Has been entered. The bias voltage generator 52 includes a PMOS 52 connected between the power supply potential Vdd and the ground potential Vss.
a and an NMOS 52b. The source of the PMOS 52a is connected to the power supply potential Vdd, and the drain of the PMOS 52a is connected to the drain of the NMOS 52b at the node N52. The input voltage V is applied to the gate of the PMOS 52a.
i is input, and the gate of the NMOS 52b is the node N52.
It is connected to the. The voltage of the node N52 is NMOS52
This is a configuration for controlling the conduction state of b. The source of the NMOS 52 is connected to the ground potential Vss.

Each of the nodes N51, 52 is connected to a transfer gate 53, 54 formed of CMOS, respectively. Further, the bias voltage generating circuit 50 includes an inverter 55 for inputting the input voltage Vi and the inverter 5
5 and the inverter 56 connected to the output side. The transfer gates 53 and 54 include an inverter 55.
And a node N51 depending on the output voltage of the inverter 56,
This is a connection for selecting the voltage of 52 and sending it to the ring oscillator 60. The ring oscillator 60 outputs the oscillation frequency f based on the input signal Vi to the output inverter 70, and the output of the output inverter 70 is the output terminal Ou.
It is output from t. The ring oscillator 60 has the same configuration as the ring oscillator in FIGS. 2 and 5, and has five stages of inverters 61, 62, 63, 64, and 65. Each of the inverters 61 to 65 has a CMOS structure, and the inverter 61 has a PMOS 61a and an NMOS 61b whose drains are connected to each other at a node N61.
Similarly, each of the inverters 62, 63, 64, 65 includes a PMOS 62a, an NMOS 62b whose drains are connected to nodes N62, N63, N64, N65, and a PMOS 62a.
63a, NMOS 63b and PMOS 64a, NMOS
64b, and a PMOS 65a and an NMOS 65b. Each node N61, N62, N63,
N64 is connected to the gate of the CMOS of the next stage as the output terminal of each of the inverters 61, 62, 63 and 64, and the node N65 is connected to the output terminal of the output inverter 70 and is the CMOS of the inverter 61. It is connected to the gates of the PMOS 61a and the NMOS 61b. Between the sources of the PMOSs 61a to 65a in the inverters 61, 62, 63, 64 and 65 and the power supply potential Vdd, the PMOSs 61c to 65c for controlling the currents flowing in the PMOSs 61a to 65a are connected, respectively.
Between the sources of the NMOSs 61b to 65b and the ground potential Vss, the NMOSs 61d to 65d for controlling the currents flowing in the NMOSs 61b to 65b are connected, respectively.
The output voltage of the node N51 or N52 selected by the bias generation circuit 50 is applied to the gates of the PMOSs 61c to 65c, and the input voltage Vi is applied to the gates of the NMOSs 61d to 65d. NMO
S61d to 65d have a configuration in which the conduction state is controlled by the input voltage Vi.

Next, the operation of the VCO shown in FIG. 1 will be described. The input voltage Vi is the NMOS 51b of the bias voltage generator 51.
Is applied to the gate of the
The resistance value of the OS 51b changes and the voltage of the node N51 changes. As the voltage of the node N51 changes, the PMOS51
The conduction state of a also changes and the voltage of the node N51 is determined. That is, the voltage of the node N51 becomes the voltage shown by the output voltage characteristic as shown in FIG. Bias voltage generator 52
Also at the same time, the input voltage Vi is applied to the gate of the PMOS 52a, and the PMOS 5 is turned on in accordance with the input voltage Vi.
The resistance value of 2a changes and the voltage of the node N52 changes. As the voltage of the node N52 changes, the conduction state of the NMOS 52b also changes and the voltage of the node N52 is fixed. The voltage of the node N52 becomes the voltage shown by the output voltage characteristic as shown in FIG. The voltage of node N51 is sent to transfer gate 53, and the voltage of node N52 is sent to transfer gate 54. On the other hand, when the level of the input voltage Vi is lower than the threshold voltage of the inverter 55, the transfer gate 53 turns on and the transfer gate 54 turns off. Therefore, the node N is connected to the gates of the PMOSs 61c to 65c in the ring oscillator 60.
The voltage of 51 is selectively supplied. When the level of the input voltage Vi is higher than the threshold voltage of the inverter 55, the transfer gate 53 is turned off and the transfer gate 54 is turned on. Therefore, the node N is connected to the gates of the PMOSs 61c to 65c in the ring oscillator 60.
The voltage of 52 is selectively supplied. FIG. 8 is a characteristic diagram showing the output voltage of the bias voltage generating circuit of FIG.

The output voltage of the bias voltage generating circuit 50 supplied to the gates of the PMOSs 61c to 65c by the operation of the transfer gates 53 and 54 becomes as shown in FIG. 8 with respect to the change of the input voltage Vi. That is, the linear region that changes linearly with the change of the input voltage Vi is wide. The ring oscillator 60 operates similarly to the first and second conventional examples. That is, the inverters 61 to 65 of each stage
The delay time is controlled by the output voltage and the input voltage Vi of the bias voltage generation circuit 50, and oscillates at the oscillation frequency f according to the control. The voltage of the node N65 that outputs the oscillation frequency f of the ring oscillator 60 is inverted by the output inverter 70 and output from the output terminal Out. FIG. 9 is a characteristic diagram showing the relationship between the input voltage of the VCO of FIG. 1 and the oscillation frequency. Since the linear region of the bias voltage sent from the bias voltage generation circuit 50 is wide, the region in which the oscillation frequency f changes linearly with respect to the change of the input voltage Vi in this VCO becomes wide. As described above, in this embodiment, the bias voltage generator 5 having different output voltage characteristics with respect to the input voltage Vi.
1, 52 are provided, and those output voltages are selected based on the input voltage Vi and are sent to the ring oscillator 60. Therefore, in the output voltage characteristic of the bias voltage circuit 50, the linear portion is widened with respect to the input voltage Vi,
Also in the oscillation frequency f of the VCO, the range proportional to the input voltage Vi is expanded. The present invention is not limited to the above embodiment, and various modifications can be made. For example, input voltage V
Two bias voltage generators having different output voltage characteristics with respect to i are used as the bias voltage generators 51 and 52, but the linear region of the VCO can be expanded by further increasing the number.

[0014]

As described in detail above, according to the present invention, a bias voltage generating section having different output voltage characteristics with respect to an input voltage is provided, and the output of the bias voltage generating section is based on the input voltage. The bias voltage is selected and sent to the ring oscillator. Therefore, for example, the output of the bias voltage generator whose output voltage changes linearly with respect to the input voltage can be selected according to the input voltage, and the output of the VCO whose oscillation frequency of the VCO changes in proportion to the input voltage. The linear region can be expanded.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a VCO showing an embodiment of the present invention.

FIG. 2 is a circuit diagram of a VCO showing a first conventional example.

FIG. 3 is a characteristic diagram showing an output voltage with respect to an input voltage of the bias voltage generating circuit of FIG.

4 is a characteristic diagram showing a relationship between an input voltage of the VCO of FIG. 2 and an oscillation frequency.

FIG. 5 is a circuit diagram of a VCO showing a second conventional example.

6 is a characteristic diagram showing an output voltage with respect to an input voltage of the bias voltage generating circuit of FIG.

7 is a characteristic diagram showing the relationship between the input voltage of the VCO of FIG. 5 and the oscillation frequency. .

8 is a characteristic diagram showing an output voltage of the bias voltage generating circuit of FIG.

9 is a characteristic diagram showing a relationship between an input voltage of the VCO of FIG. 1 and an oscillation frequency.

[Explanation of symbols]

50 bias voltage generation circuit 51,52 bias voltage generation part 53,54 transfer gate 60 ring oscillator 61-65 inverter 61a-65a, 61c-65c PMOS 61b-65b, 61d-65d NMOS Vi input voltage

Claims (1)

[Claims] 1. A bias voltage generating circuit for generating a bias voltage corresponding to an input voltage, and an output voltage of each stage of the built-in odd-numbered inverters is delayed and supplied to the next-stage inverter, respectively. A ring in which the output voltage of the inverter is delayed and supplied to the first-stage inverter to oscillate, and the delay of the output voltage of the inverter of each stage is controlled based on the input voltage and the bias voltage to change the oscillation frequency. An oscillator, comprising: a voltage-controlled oscillator that outputs a frequency corresponding to the input voltage, wherein the bias voltage generation circuit has a plurality of bias voltage generation units having different output voltage characteristics with respect to the input voltage, A configuration in which a voltage generated by the plurality of bias voltage generating units is selected as the bias voltage according to the input voltage. And, a voltage controlled oscillator, characterized in that.