JPS5879372A - Magnifying and shrinking device for image data - Google Patents

Abstract

PURPOSE:To attain mangification and shrinkage with a wide range, by providing a fraction adder summing lower-order bits of a shift register storing outputs through the use of a multiplier multiplying input image data by P and an output adder for run length signals and controlling the both. CONSTITUTION:A decoder 1 decodes a makeup code and a terminate code of the modified Haffmann code serially inputted and sets them to a register 11. A multiplier 2 multiplies the content of the register 11 with a value P stored in a register 12. A shift control 3 controls each bit of the register 14. A lower-order 6-bit of the register 14 is inputted to an adder 4 and set to a register 15 storing the preceding integrated value through addition. A carry output sets a carry storage register 16. An AND gate 6 inputs an output of the register 16 and an input of a signal line 102 and the output of an output adder 5. The adder 5 outputs the result of addition of an output value of the gate 6 to the output of the register 14 as a run length.

Description

[Detailed description of the invention] Misfire #! This invention relates to an image data 0 enlarging/reducing device used in AIri, digital fax, etc.

In a digital fax or similar system that handles horizontal scanning image data, the main scanning density and single scanning density on the sending and receiving sides must be low, respectively. Therefore, it can be easily realized by changing the sub-scanning density and changing the feeding amount of the corporate paper. However, the main scanning density is often fixed by the basic structure or circuitry of the device;
It is not easy to make it variable. On the other hand, in recent years,
There is an increasing need for electronic computers to process data that is not character coded, such as fax transmission data, and a dot printer or the like, which is an ordinary computer output device, is often used as an output device. However, in output devices for electronic computers such as dot printers, the main scanning density is non-uniform and varies, which poses a major obstacle when used as an output device for image data. That is, in order to obtain an output with the same scanning degree as the input code in a printer having a different scanning density, multiplication by a factor of several times is generally required. In other words, in order to combine image input/output devices with different main scanning densities, conventionally, a device for enlarging or reducing input image data using floating point arithmetic is required, which has the drawback of requiring a complicated circuit. There is.

In view of the above-mentioned circumstances, it is an object of the present invention to provide an image data enlarging/reducing device capable of enlarging input image data (or 1 m smaller) with a relatively simple circuit, and to The purpose is to make it easier to connect output devices.

The superposition of the present invention converts the input image data into P (a positive integer)
A multiplier that multiplies, a shift register that holds the output of the multiplier, a fraction adder that inputs the lower bits of the shift register and multiplies it with the previous input value, and a An output adder that outputs all run length signals in addition to the output of the shift register, and M! A special nod is that the JI5 is equipped with a shift control that controls the number of shifts in the shift register.

First, the principle of the present invention will be explained. The present invention is expanded (
reduction) rate M is M=P/2q ・・・・・・・・・・・・
...(1) However, scaling calculations are made easier by limiting i-' and q to positive integers. That is, integer multiples are easy, and division by 2q can be easily achieved by shifting q bits. So-
For example, the value of M obtained by using 1<P×15.0<, q×6 P and q is as shown in the table below.

As can be understood from this table, it is sufficient for practical use if multiplication and arithmetic operations involving decimal points can be easily performed and the accuracy is as high as the table above. If higher precision than the above table is required, it is possible to use the values of P and q within a larger range. However, since the output dot length is required to be Fi*tx, the fractions in the above table must be rounded down or rounded off. If the fractions due to rounding down are accumulated, the enlarged figure will be distorted. Therefore, in the present invention, the fraction is 1
By adding it to the fractions before the first order, and adding it to the run length when it exceeds 1, we decided to suppress the cumulative error to a maximum of 1 bit or less.

Next, a case in which the present invention is applied to expansion (reduction) of input data of a modified Huffman code will be described in detail. A modified Huffman code is a code established as a Gll standard for fax according to the recommendations of CCITT, and is used as a representative run-length code. This code C, the length l of one white run or black run is as follows (2
) and is a friend code.

1 = ao ten ai2 +m, 2” ten as 2'
10a42' 10m, 2'+ 2@(be + b1
2 + bt 2" + bs 2" + b42' +
bi 2)・・・・・・・・・・・・・・・(2)
However, a@~al, b, %b, is 0 or 1
It is.

In formula (2), a@-)-al 2 + at 2marojuJ 2'10a42' + at 2' =ノT...
・・・・・・(3) 2°(bs +bt2+bt2”+
bs2"10ba2'+bs2')=!tr
・・・・・・・・・・・・・・・(4)
Then, l:lT+lU. Above l! is the termination code (a・v ``1 y ''2 + is t
'4v''l), and !U above is a makeup code (b,.

k) at btt ble 1)41 k's)
It is expressed as (Actually, 64 to 2560 dots are used). In other words, a 6-bit termination code,
The run length is expressed by a set of 6-bit makeup codes. (If the run length is within 63 bits, no makeup code is required. To multiply the above-mentioned modified Huffman code by M, MA = MjT 0 MAU... Song...
...(5) can be obtained.

MA'y=-! −(ms + a1g' + at 2
” +−−zz?&s2exposure)...
・・・・・・・・・・・・−+6), so now 2@<P
<2', the numerator on the right side of equation (6) is (5+r)
It can be expressed by the following polynomial. That is, M lt = i "(a, / 10 ml'2 + - a Q
-12q-'+ a', 2(-)-・+++++++ a
'g+, 2''') = -G HCaj tenag'2+...
・+achi-, 2'l-') +(aQ+...
+a buttocks 2″+1-q) However, a, f~a′, +r are 0
or 1. Therefore, in the above formula (ao'ten at'2
＋−・・・・・・10a −, 2q−”> / zz−”
must be a fraction less than 1, (a', +"-+ a'6+,
2''-q) is zero or a positive integer.

R= ao'+ a, #2 + ...-+a4
If we rewrite the above equation by setting −12Q″″1, we get Ml! -F+(a,'+...-...+aK+r2s+
r-q)・・・・・・・・・・・・・・・(7)(7)
R/2q in the formula is a fraction.

On the other hand, MjU:! 7・2・(bo+kls2+・・・・・・・
...+b, 2") = 2'-q(b,: + b
, '2 + ・・−・・−・−・−・−+ b%+,
2'')...... (8) Therefore, if q is an integer of 6, then equation (8) is zero or a positive integer.

From formulas (7) and (8), Ml = ][1+ (aQ+−・−・−・−・ten’s
ay 2 ”””') + 26 - cheers (bs +・--=
+ b lI + r 2 ”' )・・・・・・・・・
......(9) In equation (9), R/2q is a fraction, so the new run length l' is expressed as: 1 = Ml - R/24 ; (1'...・+'S+r2) Music+2'-q(be+・・・・・・・・・+b4,21
i+r)・・・・・・・・・・・・・・・-・Q groan,
When the cumulative fraction R/2q exceeds 1, 1 can be added to the run length j' to prevent the accumulation of errors. Of course, the accumulated result less than 1 is retained and further accumulated with the next fraction.

Next, a specific example in which the present invention is applied to a modified Huffman code will be described. The figure is a block diagram showing one embodiment of the invention. Well, decoder 1. Multiplier 2. Shift control 3. Fraction adder 4. Output adder5. AND Gate 6 and registers 11-1 in each building
It consists of 6. Register 14 is a shift register.

The decoder 1 sequentially decodes the make-up code and termination code of the serially input modified human code and stores them in the register 11. Multiplier 2 multiplies the contents of register 11 by value P held in register 12 and sets the result in shift register 14 . Register 12 above
ti (register that holds P in equation 11, now P = 1
Assume that it is set to 5. Also, q in equation (1)
is held in the register 13 and is currently set to q-=6. The shift control 3 controls shifting of each bit of the shift register 14.

The adder 4 inputs the lower 6 bits of the shift register 14, adds it to the contents of the register 15 that holds the previous cumulative value, sets the addition result in the register 15, and sets the carry holding register 16 as a carry output. . The AND gate 6 inputs the output of the carry hold register 16 and the signal line 102, and sends the output to the output adder 5.The output value of the AND gate 6 is added to the output of the output adder 5F'i shift register 14. Output the result as run length.

Next, the operation of this embodiment will be explained. First of all, 4 children 10
A make-up code of a modified Huffman code is received from 1, decoded by a decoder 1, and set in a register 11. The output of register 11 is multiplied by P by multiplier 2. Since the output #'i of register 11 is 6 bits and the register 12 is 4 bits (because 15<2'), the output of multiplier 2 is a maximum of 10 bits. Since the make-up code is now 1/64 of the run length, the output of multiplier 2 must be multiplied by 26 to convert it to the run length. Since it has to be divided by 2q, the shift control 3 ultimately shifts 6-q bits toward higher-order digits.

The output of the shift register 14 is output from the terminal 103 through the output adder 5. The signal 102 is "Calculating cup code /l1IIO", and there is no output from the AND gate 6.

Next, a termination code is input manually from the terminal 101, decoded by the decoder 1, and set in the register 11. The output of the register 11 is doubled by the multiplier 2 to become an output with a maximum length of 10 bits, which is set in the register 14. Since the contents of register 14 must be divided by 2q, the lower q bits correspond to the fraction R/2q in equation (7). So (6
-q) If the bits are shifted toward the higher digits, the lower 6 digits will represent a fraction. Therefore, the shift controller 3 shifts the contents of the shift register 14 by one (fi-q) bit in the direction of the higher digits, and sends the lower 6 bits to the adder 4. A 6-bit register 15 connected to the output of the adder 4 has previously added fractions and accumulated nine fractions. Then, adder 4 adds the contents of register 15 and the above input, and stores the lower 6 bits of the addition result in register 1.
5, and the carry holding register 16 is set by the carry. Next, the contents of the register 14 are shifted by 6 bits toward the lower digits by the shift control 3 (at this time, the least significant digit becomes the first digit). Thereafter, the output of register 14 is sent to output adder 5. Since the AND gate 6 is opened by the signal line 102 at this time, +1 is added when the carry holding register 16 is set, and if there is no carry, the signal is output from the output terminal 103 as is. As a result of the above operation, the output terminal 103 first outputs M (=P/2') times the run length corresponding to the make-up code, and then outputs M times the run length corresponding to the termination code, rounding down the fractions. . The rounded fractions are then accumulated in a fraction adder 4, and when they reach 1, they are added to the run length. Therefore, according to this embodiment, wide-range magnification and reduction can be realized with a relatively simple circuit.Furthermore, fractions less than 1 bit are accumulated for each run length, and when the number exceeds 1 bit, the run length is immediately changed. The cumulative error is at most 1 bit.

As described above, in the present invention, the magnification of the input value is M=
By using P/2q, the output value is obtained by multiplication of integers and shift operation of the shift register, so it is possible to perform enlargement and reduction by a wide range of magnifications with a relatively simple circuit. . In addition, since fractions less than 1 bit are accumulated and output is added to the run length when the accumulated value reaches 1 bit, distortion of the figure due to accumulated errors is small. Therefore, it has the effect of facilitating the combination of image data output devices having different main scanning densities.

[Brief explanation of drawings]

The figure is a block diagram showing one embodiment of the present invention. In the figure, 1...decoder, 2...multiplier, 3...
...Shift control, 4...Fraction adder, 5...
- Output adder, 6...AND gate, 14...shift register. Representative Patent Attorney Sumi 1) Sou Toshi

Claims (1)

[Claims] A multiplier that multiplies the input image data by P (positive! an output adder that adds the carry of the fraction adder to the output of the shift register and outputs a run length signal; and a shift control that controls the number of shifts of the shift register. Data scaling device.