JPS58213377A - Picture processor - Google Patents

Abstract

PURPOSE:To attain the operation at high speed with less operating bit width, by providing a fixed decimal-point operating circuit comprising a shifter shifting a data from a bus line via a gate for matching it into a required data width and a shifter matching the result of operation to the bus line. CONSTITUTION:The content of operation of an operating device 8 is functions such as addition and multiplication and an input data from a bus 7 is outputted to a bus 9 after the operation. When this output passes through the shifter 10, the inverted operation to the input shifter 5 is done and the amount of bits to be shifted is the same as that of the shiter 5 at the addition and as twice as that of the shifter 5 at the multiplication, which is controlled with an output shifter control signal from a control logic 15. Thus, the data outputted on an internal output bus line 12 through the shifter 10 has the decimal-point at the same location as that of the bus line 1 and outputted on the bus line 1 through a gate 13 with the control signal and the operation is finished.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an arithmetic circuit for image processing, and particularly to speeding up arithmetic operations on image data attached to an image memory.

Conventionally, various attempts have been made to speed up arithmetic circuits, each with its own characteristics. Many of these general data processing circuits are called floating point type in order to maintain accuracy, and the data itself has decimal point position information, and this decimal point alignment causes deterioration in processing speed. Ta. Also, fixed-point types are fast, but unless the data bit width is made considerably larger to maintain accuracy, overflow occurs and calculations become impossible, resulting in large-scale and large-scale operations. Speed deterioration due to this was unavoidable.

Considering the special characteristics of data operations in image processing, the precision of all data is 8-bit integers, and the precision of other parameters is also real numbers that can be converted into 16-bit fixed-point numbers at most. There is a remarkable feature that there is. In addition, there is a feature that the number of repetitions of the calculation is 105 to 7 times, which is the same as the amount of image data, which greatly affects the speed.

The present invention is an example of reviewing and considering the arithmetic circuit from a different perspective for these reasons.

Therefore, an object of the present invention is to provide an arithmetic circuit suitable for an image processing apparatus in which problems arise in response and economy when conventional arithmetic circuits are mounted.

A specific object of the present invention is to provide a high-speed and effective arithmetic circuit with a small arithmetic bit width, taking into consideration the difference between image data processing and general data processing.

Another object of the present invention is to provide an inexpensive image data arithmetic circuit that relies on reducing the circuit scale.

Still another object of the present invention is to speed up data calculation in image processing data processing and improve responsiveness of an interactive image processing device.

The above-mentioned aspects of the present invention include a pass line having a fixed point through which image processing data passes, a gate circuit connected to the pass line for input/output of an arithmetic circuit, and a gate circuit provided from the outside for arithmetic control. a register that holds data,
This is achieved by an image processing device having a shifter that shifts data from the pass line to match the required data width, and a fixed-point arithmetic circuit having a shifter that matches the calculation result to the pass line. .

The image data calculation circuit according to the present invention has the ability to perform maximum likelihood discrimination calculations used in remote sensing, etc. in an extremely short time of about 5 seconds per category, so it is suitable for digital images for these applications. It is expected that this will have a significant effect on speeding up conversation processing in image analysis in processing systems.

The content of the present invention will be described in detail below.

Data used in image processing is different from general data in that it has a 3-bit integer precision, and other parameters given are real numbers that can be represented by a 16-bit fixed point number at most.

In addition, in order to use this processing result for display, it should be 8 bits.
If the result is to be used in some type, it only needs to be 24 bits wide. For this reason, compared to general data arithmetic circuits,
It becomes possible to fix the decimal point position on the path line. However, theoretically, the width of the calculation g b i is required to be about 48 bits, but in the present invention, it is possible with a width of 24 bits.

Next, a preferred embodiment of the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, reference number 1 is a pass line with a width of 24 bits, and there is a decimal point between the 9th bit and the 10th bit from the top. The data on this path line 1 is taken into the internal bus 4 via the gate 2 according to the gate control signal 3 output from the control logic, and the data on the internal operation bus 7 is taken into the internal bus 7 according to the shift control signal 6. The data is output as data shifted by the number of ITs as necessary using a shifter. The contents of the operations performed by the arithmetic unit 8 are functions such as addition and multiplication), and the data inputted to the bus 7 is operated by the arithmetic unit 8 and then output to the bus 9. The data output to the bus 9 is operated in the opposite way to that of the input shifter 5 when it is added to the 10 shifters, but the amount of bits to be shifted depends on the content of the operation. During multiplication, it is controlled by the output shifter control signal 11 from the control logic 15 so as to shift twice the amount of the shifter 5. As a result, the data passed through the shifter 10 and outputted to the internal output bus line 12 has a decimal point at the same position as the pass line 1, and depending on the control signal 14, the data passes through the gate 13 and is output to the pass line 1. 1 and the calculation ends. At this time, the arithmetic unit 8 has a length of 24 bits, and if the arithmetic operation is performed with a fixed length, there is a possibility that overflow will occur after three multiplications, but if the input shifter 5 shifts 8 bits to the LSB side, the overflow The purpose is achieved by shifting the output by 16 bits using the output shifter 10. Of course, it is possible for the output shifter 10 to cause an overflow, but in image processing, the output value range can be limited, so overflow=the maximum output value. As a result, it is expected to be twice as fast as a similar floating point operation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1... Pass line, 2... Input gate, 3... Input gate control signal, 4...
・Internal human power bus line, 5... Input shifter, 6
...Input shifter control signal, 7...Calculation manual path line, 8...Arithmetic unit, 9...
・Calculation output bus line, 10-...output shifter,
11... Output shifter control signal, 12...
・Internal output pass line, 13...output gate,
14... Output gate control signal, 15...
・Control logic patent applicant Nichifu Electric Co., Ltd. Agent Patent attorney Yutabu Kumagai 1m

Claims (1)

[Claims] a pass line having a fixed point; a gate connected to the pass line; a control register that inputs data from the outside; and a shifter that shifts data from the pass line through the gate according to the contents of the register; An image processing device characterized by having a fixed-point arithmetic unit that inputs and outputs data that has undergone this thick processing.