JPS5878638U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS5878638U
JPS5878638U JP17435481U JP17435481U JPS5878638U JP S5878638 U JPS5878638 U JP S5878638U JP 17435481 U JP17435481 U JP 17435481U JP 17435481 U JP17435481 U JP 17435481U JP S5878638 U JPS5878638 U JP S5878638U
Authority
JP
Japan
Prior art keywords
semiconductor chip
chip fixing
lead
semiconductor device
semiconductor equipment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17435481U
Other languages
English (en)
Other versions
JPS6339970Y2 (ja
Inventor
川口 晃充
Original Assignee
新電元工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 新電元工業株式会社 filed Critical 新電元工業株式会社
Priority to JP17435481U priority Critical patent/JPS5878638U/ja
Publication of JPS5878638U publication Critical patent/JPS5878638U/ja
Application granted granted Critical
Publication of JPS6339970Y2 publication Critical patent/JPS6339970Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第1図は本考案半導体装置の構造斜視図、第2図a”−
dは本考案半導体装置の製造工程図である。 1は樹脂部、2は半導体チップ固着部、3はコネクタ接
続部、4は半導体チップ、5はコネクタ線1、E、B、
Cはリード片をしめす。

Claims (2)

    【実用新案登録請求の範囲】
  1. (1)半導体チップ固着部を有するリード片及びコネク
    タ接続部を有するリード片を夫々1又は複数個並置し、
    相隣る上記リード片間を結合し、且つ該半導体チップ固
    着部及び該コネクタ接続部を含んで封止するごとく樹脂
    部を設け、該樹脂部を上記リード片の厚さ及び長さとほ
    ぼ等しい範囲に形成したことを特徴とする半導体装置。
  2. (2)各リード片に凹部を設け、半導体チップ固着部又
    はコネクタ接続部とした実用新案登録請求の範囲第1項
    記載の半導体装置。
JP17435481U 1981-11-24 1981-11-24 半導体装置 Granted JPS5878638U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17435481U JPS5878638U (ja) 1981-11-24 1981-11-24 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17435481U JPS5878638U (ja) 1981-11-24 1981-11-24 半導体装置

Publications (2)

Publication Number Publication Date
JPS5878638U true JPS5878638U (ja) 1983-05-27
JPS6339970Y2 JPS6339970Y2 (ja) 1988-10-19

Family

ID=29966331

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17435481U Granted JPS5878638U (ja) 1981-11-24 1981-11-24 半導体装置

Country Status (1)

Country Link
JP (1) JPS5878638U (ja)

Also Published As

Publication number Publication date
JPS6339970Y2 (ja) 1988-10-19

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