JPS5862723A - デ−タ転送制御装置 - Google Patents

デ−タ転送制御装置

Info

Publication number
JPS5862723A
JPS5862723A JP16016281A JP16016281A JPS5862723A JP S5862723 A JPS5862723 A JP S5862723A JP 16016281 A JP16016281 A JP 16016281A JP 16016281 A JP16016281 A JP 16016281A JP S5862723 A JPS5862723 A JP S5862723A
Authority
JP
Japan
Prior art keywords
data
byte
word
input
byte position
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16016281A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0122941B2 (enExample
Inventor
Isamu Yasui
勇 安井
Etsuo Masuda
増田　悦夫
Tomiji Hara
原　富治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
NTT Inc
Original Assignee
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Nippon Telegraph and Telephone Corp filed Critical Hitachi Ltd
Priority to JP16016281A priority Critical patent/JPS5862723A/ja
Publication of JPS5862723A publication Critical patent/JPS5862723A/ja
Publication of JPH0122941B2 publication Critical patent/JPH0122941B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
JP16016281A 1981-10-09 1981-10-09 デ−タ転送制御装置 Granted JPS5862723A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16016281A JPS5862723A (ja) 1981-10-09 1981-10-09 デ−タ転送制御装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16016281A JPS5862723A (ja) 1981-10-09 1981-10-09 デ−タ転送制御装置

Publications (2)

Publication Number Publication Date
JPS5862723A true JPS5862723A (ja) 1983-04-14
JPH0122941B2 JPH0122941B2 (enExample) 1989-04-28

Family

ID=15709198

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16016281A Granted JPS5862723A (ja) 1981-10-09 1981-10-09 デ−タ転送制御装置

Country Status (1)

Country Link
JP (1) JPS5862723A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6210756A (ja) * 1985-07-09 1987-01-19 Fujitsu Ltd 複数プロセツサ間の通信方式

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6210756A (ja) * 1985-07-09 1987-01-19 Fujitsu Ltd 複数プロセツサ間の通信方式

Also Published As

Publication number Publication date
JPH0122941B2 (enExample) 1989-04-28

Similar Documents

Publication Publication Date Title
JPH0146892B2 (enExample)
EP0689208A1 (en) Method for block oriented addressing
JPS5862723A (ja) デ−タ転送制御装置
CN100357920C (zh) 平行输入/输出数据传输控制器
JPH07210468A (ja) 半導体補助記憶装置
CN111045961B (zh) 数据处理方法及使用所述方法的存储控制器
JPS6336008B2 (enExample)
WO1985003372A1 (fr) Systeme de transmission/reception de donnees permettant de transmettre des donnees en direction et en provenance d'un organe de memoire auxiliaire
JP2783042B2 (ja) Ｄｍａ転送回路
JPS58169398A (ja) メモリ・システム
JPS6124737B2 (enExample)
JPS6053326B2 (ja) 入出力制御装置のデ−タ２重記録方式
JPS6047626B2 (ja) デ−タ・バッファ制御方式
JPS5854478A (ja) 主記憶制御方法
JPH0196734A (ja) スタック制御装置
JPS63224487A (ja) デイジタルデ−タレコ−ダ制御装置
JPS6127780B2 (enExample)
JPH02133854A (ja) 転送可否メモリにアクセス可能なｄｍａコントローラ
JPH0327462A (ja) 高速フアイル制御装置
JPS58201158A (ja) デ−タ保存処理システム
JPS63229558A (ja) 直列信号インタフエ−スによるデ−タ転送装置
JPS6021654A (ja) バツフアメモリ
JPH0122655B2 (enExample)
JPS61193230A (ja) 磁気デイスク制御装置
JPH04148351A (ja) ディスクキャッシュ制御装置