JPS5852844A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable to obtain high degree of integration and to perform a high- speed operation for the titled device by a method wherein the interval of a buried region is reduced by preventing the contact of depletion layers. CONSTITUTION:An n<+> buried collector region 2 is provided on the main surface of a p type substrate 1 by selectively diffusing arsenic, and after an n type epitaxial layer 3 has been formed, an insulating oxide film 4 is selectively buried in the epitaxial layer 3. The ion implantation by boron which will be performed immediately before the formation of the oxide film 4 is to be performed in two steps. The channel stopper region 15 which was formed under the above condition of ion implantation is formed at approximately 1.7mum in depth from the bottom face of the oxide film 4. In this kind of constitution as above, the depletion region 16 extending on the substrate 1 from the collector region 2 is suppressed by the channel stopper region 15, and is not formed on the part which has the curvature of junction of the buried collector region. As a result, the interval of depletion layers is sufficiently aparted, and there exists no possibility of their coming into contact with each other.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides ili! Bipolar semiconductor integrated circuit device C and below that enables high-speed operation with i integration density, B 1
(referred to as p-IC).

Conventionally, in Bip-ICE, a structure in which a thin epitaxial layer is separated by a thick oxide film is being introduced for the purpose of higher integration and higher speed. Here, the width of the isolation region between elements is one of the important factors that determines the density.
If the thickness of the epitaxial layer is constant, d, this width is determined by the spacing between the buried collector regions. However,
Conventionally, the channel stopper region provided directly under the insulating oxide film has been formed to be much shallower than the buried collector region. For this, the built-in voltage that occurs at the junction between the buried collector and the substrate is approximately 1 μm1! The depletion layer extends toward the substrate side. Furthermore, during actual device operation, since the junction is biased with a power supply voltage, the expansion of the depletion layer further increases. In such a case, if depletion layers extending from adjacent buried collector regions come into contact with each other, isolation between elements is no longer achieved.

FIG. 1 shows a conventional integrated circuit device. In FIG. 1, an N+ type buried collector region 2 is provided by selectively diffusing arsenic onto the main surface of a P type substrate 1 having a specific resistance of approximately 15 Ω·1. The junction depth of the buried collector region 2 is about 2 μm. Then N
After providing the type epitaxial layer 3, an insulating oxide film 4 is selectively epitaxied to form a Pg channel stopper region 5 at the same time. Conventionally, this channel stopper region has a depth of 0.3 μm and 11 degrees from the bottom surface of the oxide film 4. Due to this, the depletion layer region 6 extending from the buried collector region 3 to the substrate 1 becomes in contact with each other as shown in FIG. The limit spacing between the buried collector regions on the mask at which such contact occurs is based on the lateral diffusion (approximately 2 μm) of the buried collector IgA and the expansion of the depletion layer (approximately 1 μm), assuming that only the built-in voltage is biased. The sum of both amounts is approximately 6pm. For this reason, masks are designed to be worn at 7 μm intervals near the dormitory, allowing for extra space.

An object of the present invention is to provide a bipolar semiconductor integrated circuit device that can reduce the distance between buried collector regions by preventing contact between the depletion layers described above, and can therefore achieve high integration and high-speed operation. In the semiconductor integrated circuit device of the present invention, each element forming region is separated by an insulating isolation oxide, and a channel stopper region is provided directly under the insulating isolation oxide, and this channel stopper region It has a configuration in which the collector area is leaked from the collector area.

Next, the present invention will be explained using examples.

FIG. 2 is a sectional view of one embodiment of the present invention. In FIG. 2, an insulating oxide film 4 is buried in a buried collector region 9 on the mask with a thickness of 6 μm through the same process as explained in FIG. At this time, the conditions for the ion implantation of hydrogen immediately before forming m@4 were 400 KeV acceleration energy and % 5X.
10"~5X10"110 dose, and 150KeV
With acceleration energy of I x 1011~1 x 10”
Two-stage implantation is performed at a dose of cm-. The purpose of the implantation conditions is to compensate for the lack of boron concentration directly under the oxide film 4. The channel stopper region 15 formed under such ion implantation conditions is approximately 17 μm from the bottom of the oxide film 4.
formed at a depth of In such a structure, the nine depletion region 16 extending from the buried collector region 2 into the substrate 1 is
As shown in the figure, it is suppressed by the sufficiently deep channel stopper region 15 and is hardly formed in the curved portion of the junction of the buried collector region. For this reason, there is sufficient distance between the depletion layers as shown in the diagram, and the fear of contact is eliminated.

As described above, according to the present invention, it is possible to further reduce the interval between embedded collector regions than in the conventional structure, and it is possible to obtain a Bip-IC that can perform high-density and high-speed operation. .

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a conventional semiconductor integrated circuit device. FIG. 2 is a sectional view of one embodiment of the present invention. l...P-type silicon substrate, 2...N
Gluing; Rector region, 3... Nll epitaxial layer, 4... Insulating isolation oxide film, 5.15...
... PrI! Channel stopper area 16*16...
...Depletion layer. +7 Team Z

Claims (1)

[Claims] In a by-diller type semiconductor integrated circuit device having an oxide insulation isolation structure, a channel stopper region provided directly under the insulation oxide of the insulation isolation is buried adjacent to the rectifier region.
The shallow ◆ is 4! Semiconductor integrated circuit device.