JPS5851536A - Master slice chip - Google Patents

Abstract

PURPOSE:To simultaneously satisfy the difficult compatible conditions such as low power consumption, high speed and high density by providing a plurality of gate arrays having different gate widths on the same chip. CONSTITUTION:A master slice 1 has the first gate width region 3, the second gate width region 4 and the third gate width region 5, and the gate widths of the gate arrays formed on the respective regions are, for example, set to the relationship of (the first gate array width)<(the second gate array width)<(the third gate array width). The respective gate regions can be formed of an element region 1a and a wiring region 1b. In this case, the gate widths between the regions 1a in each gate width region can be set to different values.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gate array integrated circuit, and more particularly to a mask sliced chip having gate arrays with gate widths of %% different.

A master slicing method is known in which integrated circuits are made exactly the same up to the last metal evaporated wiring, and integrated circuits having different functions are manufactured by changing only the last metal evaporated wiring. In such an i-star slice integrated circuit.

The element area where electronic circuit elements are arranged on the l-step and the wiring area for wiring between these elements are determined in advance, and the mask slices after the diffusion process (sea urchin fly level) are different for each product. Wire each other using the wiring pattern
sI acid formation. Therefore, the master slice satisfies the requirement for optimum integration density, and has the advantage of being highly flexible in that circuit design can be made according to customer orders.

The structure of a typical master slice step 1 is shown in FIG. As shown, the master slice chip IFi,
Roughly, it has a cable region 1m, a wiring region 1b, and a peripheral region 1c as an I10 buffer radial portion, and each of these regions is divided and formed on the semiconductor substrate.

1A child area 1aK: #1 MO8) A large number of electronic circuit elements such as transistors are arranged in a row, and the gates of the MOS transistors constitute a gate array.

Wiring area 1b#i is an area where wiring is performed to connect elements in the element area la to form a functional block, and there are a plurality of underpasses (buried wiring layers) 2 extending laterally. Line play is busy @ these underbus 2 is 1 normal.

It is formed as a diffusion layer of polycrystalline silicon or P0 diffusion or N0 diffusion. On the other hand, the vertical metal wiring in the wiring region 1b is formed on the insulating layer KA on the underfemale 2.
1. It is formed by vapor deposition of metals such as.

By the way, in conventional master slice chips, the gate widths of the gate arrays formed in the element area are the same, and since the ability to drive the input/output buffer is required, the gate widths are not set too small. It was impossible to do so. Therefore, if a circuit for high-speed operation is configured with a gate array, a considerable amount of switching current may flow even if CMO8i is used.

Therefore, the unit gate area cannot be reduced below a certain level, and there is a limit on the degree of integration.

The present invention was developed in view of the above points, and it makes it possible to simultaneously satisfy the difficult conditions of low power consumption, high speed, and high density, and provides flexibility in the circuit configuration of a single machine. Aims to provide master slicing chip tubes. That is.

The present invention provides a master slice chip having a plurality of device regions and a wiring region interposed between the device regions and connecting the device regions, wherein each device region includes a gate array having a predetermined genit ring. Moreover, at least one element region is characterized in that it has a gate interaction with a value different from that of the other element regions.

Hereinafter, one specific embodiment of the present invention will be described with reference to one drawing. The master slice l of the present invention can also be based on the same Sakaki construction as the typical example shown in FIG.
In this case, several MO8 structures are formed in a gate array formed in an array in a device area 1 m, and the gate @i in at least one element iii has a gate width within the gate width of another element *. Figure 2 is a schematic diagram showing another embodiment of the present invention, in which the mask slice l is set to different values from the first gate width region 3°8I2 gate width region 4%. The gate array has a gate width region 5, and the gate width of the gate array formed in each region is set such that, for example, the first gate width<the second gate width>the third gate width.

Each gate width region can be composed of an element region 1a and a wiring region 1b, for example, as shown in FIG.
In that case, it is also possible to set the gate widths between the element regions 1a in each gate width region to different values.

FIG. 3 shows the gate array t formed in each gate width region.
This shows an example of a case where it is formed with a cMO8 structure.

As shown in FIG. 3, for example, a KP well (not shown) in an N-type substrate is formed with gold diffusion.

An N+ diffusion layer 6 as a source/drain region is formed in the P well, and a P+ diffusion layer 7 is formed in the substrate. The N10 diffusion layer 6 and the P10 diffusion layer are each shown in a 3il area, but 1. These function as sources or drains, respectively, depending on how they are connected to the power supply and attached circuits.

Substrate surface K on which N0 diffusion layer 6 and P10 diffusion layer 7Yr are formed
An insulating layer is formed on the insulating layer, and a control gate is formed on the insulating layer.
8 is formed. The control gate 8 is 1. Adjacent source/drain regions (6 or 7) in the gate length direction
), and has a gate width Wt- in a direction perpendicular to the gate length. Figure 3 CMO
When the master slice lt- shown in FIG.

The relationship between the second gate width region 4 (G) 41W2 and the third gate width region W3 is Wl(W2(W3).

To give an example, W1=10μ.

It is possible to set W2 = 20μsn and W3 = 40μsn.

Incidentally, when the gate width is increased, the gate delay becomes smaller if the load capacitance is the same, but the source/drain area also increases accordingly, so the load capacitance increases. Therefore, as long as the game It drives the same gate width as itself, the game F
The delay remains almost the same. On the other hand, when driving an output buffer with a large gate width using a small gate (I wonder if the gate width is large), it is better to cascade several stages of gates with gradually larger gate widths than to drive with a single stage of gates with a smaller gate width. It is possible to make the delay tube smaller as a whole. Therefore.

By constructing a plurality of gate arrays with different gate widths on the same chip as in the present invention, it is possible to easily satisfy such requirements. That is, in the mask slice I shown in FIG. 2, the main circuit portion that operates at high speed is constituted by the first gate width region 3 with the minimum dirt width, and the input/output gates to the region 3 are constituted by the second gate width region 3 having the intermediate gate width. It is possible to configure the gate width region 4 and connect gates between the region 4 and the I10 buffer peripheral region 1c to configure the third gate width region 5 having the largest gate width. With this configuration, one chip can achieve low power consumption and
High speed.

It is possible to simultaneously satisfy contradictory requirements such as high density.

As described in detail above, according to the present invention, by providing a plurality of gate arrays having different gate widths on the same chip, it is possible to provide a master slice chip with improved performance. Note that the present invention is not limited to the specific embodiments described above, and it goes without saying that various modifications can be made within the technical scope based on the claims.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram showing the structure of a typical master slice chip, Fig. 2 is an explanatory diagram showing one embodiment of the invention, and Fig. 3 is an explanatory diagram showing a case where the gate array is configured with a t-CMO8 structure. Figure. (Explanation of symbols) 1: Master slice chip 1a: Element area lb = wiring dtA clay W: Gate width Patent applicant Rico Co., Ltd. -

Claims (1)

[Claims] 1@In a mask sliced chip having several device regions and a wiring region interposed between the device regions and connecting the device regions, each of the device regions is provided with a gate array having a predetermined gate width. At least one element area has a different value than other element areas) @1
A mask slice chip with a grain and a 1* character.