JPS5850802A - Multifrequency digital sine wave generator - Google Patents

Abstract

PURPOSE:To obtain a multifrequency digital sine wave without scaling up circuit constitution by generating digital sine waves differing in frequency on time- division basis within a prescribed period, and adding them. CONSTITUTION:In a digital sine wave generator 20, frequency set values Fa and fb are added by an adder 22 and integrated in registers 23 and 24 through switches 21A and 21B within two time intervals t1 or a period T, and the contents of the registers are sampled by a clock fc and read in an ROM25 to generate digital sine waves Sa and Sb on time-division basis. This signal sequence (a) is delayed by t1 at a delay circuit 29 through an attenuator 26 to obtain a signal sequence (b), which is added to the signal sequence (a) by an adder 30 to obtain a signal sequence (c). A switch 31 outputs only the signal sequence (d) in the latter half time t1 of the period T. Thus, the multifrequency digital sine wave consisting of sine waves Sa and Sb is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multi-frequency digital sine wave generator that simultaneously generates a plurality of digital sine waves of different frequencies.

FIG. 1 is a block diagram showing an example of a conventional multi-frequency digital sine wave generator.

In this figure, digital sine wave generation ill is performed by adder 2. It consists of a register 3 and a ROM (read-only memory) 4, and the frequency setting value F applied to the input terminal 5 is cumulatively added at the clock frequency f by the addition 612 and the register 3, and a digital sine wave is generated. The address of the ROM 4 is specified for each clock so that the frequency is f, and a digital sine wave S of frequency f is read out and generated. This digital sine wave S is generated by a digital attenuation s16 composed of a multiplication unit and an attenuation amount setting unit TlI composed of an I10 port of an I/P booster.
After the level is adjusted by C, add it! Added to one end of Ilu. Further, the digital sine wave generator 9 generates an addition −1
0, register 11 and ROM 12,
Add the frequency setting value F applied to the input terminal 1s1)
10 and register 11, the digital sine wave Sh of frequency fb is added by specifying the 7 addresses of 110M12 to each px so that the digital sine wave becomes frequency f. is read and generated.

This digital sine wave 8b is transmitted through the digital variable attenuator 1.
4 and the level is adjusted by the attenuation setting l1ls, the addition I! @ is added to the other end.

Therefore, a digital sine wave S with a frequency f and a digital sine wave S with a frequency f are simultaneously output from the adder, and a digital sine wave 8m+8b with two different frequencies is generated from the output terminal 1e. .

However, according to the above conventional configuration, digital sine liquids with different frequencies 1 are generated by the same circuit, and multi-frequency digital sine liquids are generated by adding them. The same digital sine wave generator and digital attenuator are required for the same number of frequencies.This invention was made in consideration of the above problem, and it is possible to time-divide 11Cn digital sine waves of different frequencies within a predetermined period. The digital sine liquid that is repeatedly generated in a predetermined period and is sequentially delayed by n-1 @ and the digital sine wave that has been delayed and the digital sine wave before being delayed are added, and the summed n sine waves are obtained. The present invention provides a multi-frequency digital sine wave generating device that simultaneously generates either n digital positive arc waves within the same cycle or within different cycles.

The invention will be explained below with reference to the drawings.

FIG. 2 is a configuration diagram showing one embodiment of the present invention, and FIG.
This figure is a time chart for explaining the operation of the embodiment shown in FIG.

In FIG. 2, 20 is a digital sine wave generator, switchers 21A, 21B, adder 22. register! 1.24
．． and ROM2S, with a period r(t,
10t, ) respectively within time t□.

t, (t,"t,,"7) sequentially different frequencies f
Generate two digital sine waves of a # 'b, and apply these two digital sine liquids to Km for each of the turbidity jllT.
Occurs in return. 26 is a digital attenuator, which generates a digital sine wave 11! * Receive digital sine waves 8mm 8k of frequency f, , f- outputted from *, and adjust the level of each digital sine liquid at the time 1. ．． 1. The adjustment is repeated every cycle T. 2T is definitely installed! In the section, the digital attenuator 2s is operated for the said time 1m, 1. In order to adjust the level of the digital sine liquid that is repeatedly generated at each period T, a predetermined amount of attenuation is set respectively.
The signal is switched to the period T by 1 and applied to the digital attenuator 26. 2- is a transporter which delays the digital sine liquid 8as8k of the frequency afa-tb whose level has been adjusted by the digital attenuator 26 by the time t8. 3
・is an adder.

The output of the digital attenuator 1s and the output of the delay tube lll- are connected at the time 1. ．． 1. Add and output each time.

The third bit is a switch, and the frequency fa added by the addition SSO
* Of the digital sine waves 8a*8 of fb, only the digital sine wave of frequency faefb added at the final time in the period T, that is, time t8, is switched and detected, and Simultaneously outputs two gauge sine waves sa + 8b. 32 is a signal generator for driving the switching device, which has a half width of 5etIb (tl-tt
) is repeatedly generated.

! 13. $4 is an input terminal, and 3s is an output terminal.

Next, the operation will be explained with reference to the time chart t in FIG.

Time tIK switch 21A within period T is connected to input terminal 3s,
Further, the frequency setting value F, which is applied to the input terminal 33 by switching the switch 21B to the register 2s, is transferred to the adder 2
2 and the register 23 at a frequency f, and designate the address of the ROM 2S as each p so that the digital sine wave has a frequency f.

A digital flat sinusoidal wave SIh is read out and generated. Thereafter, at time t within the period T, the switch 4111 is switched to the input terminal 34, and the switch 21B is switched to the register 24, and the cycle m added to the input terminal $4 is switched to the register 24.
Adding the number setting value Fk -22 and register 24 sets the frequency f.

is the opposite-phase Kutsk frequency 7. with a phase difference of 1800.
Then, a digital sine wave 8b of frequency f- is read out and generated by designating each 7F-less clock of the ROM 25 so that the digital sine wave has frequency rb.

If the digital sine wave S,, S- occurs in the first period T, 8al@8b1 e, 1 occurs in the second period T, 86g m s;
...; If it occurs in the mth cycle, Saw @
8bwa, as shown in the aml (@), from the digital sine wave generation SZO, within the period T, the time 11.
1. Sequential digital sine wave S□e s, ;B
The digital sine wave generation 112 is repeatedly generated as follows: q e 8% @ s... Digital attenuator 2@, attenuation amount setting section 2
7. and change the respective sine wave levels at times 1, . 1. After the adjustment is repeated every cycle T, the delay 112@ is added and the delay is delayed by a time t1 as shown in FIG. 3(b). This delayed digital sine wave L m ak and the digital positive arc wave 81 . S- to the adder 30, time 1m, 1
．． and outputs a digital sine wave as shown in Figure 3 (1).

By repeatedly selecting only the digital sine wave added to the one-hour tone out of this digital sine wave by the switch 31 for a time period t,
), the two digital sine waves with the same period are output from the output terminal 35 simultaneously and intermittently at every period T, resulting in two-frequency digital sine waves s, +
Generated as sb.

In the above embodiment, two digital sine waves having the same cycle are generated, but it is also possible to generate digital sine waves having different cycles. Furthermore, the digital sine waves that are generated at the same time have two frequencies (tc), but it is possible to generate digital sine waves with more than two frequencies by adding a delay device and an adder. Furthermore, the generation time t of the digital sine wave of each degree frequency (a is 1 or 2)
are not necessarily the same and may be different, and the delay time t is the generation time t of the sinusoidal wave of the surrounding fluid,
It is not necessary to match the generation time t1, and it may be shorter than the generation time t1. In the above embodiment, the switching devices 21A and 21B
, 28, 314 tu and 1t, but these can also be performed using a circuit using AND and OR, and the switch 31 #switch drive signal generator 32 is as shown in FIG. It is also possible to provide it on the receiving side instead of on the transmitting side.

As explained in detail above, according to this generator, n digital sine waves of different frequencies are generated in a time division manner for a desired time each within a predetermined period, and after being repeatedly generated at each predetermined period, , the digital sine wave that has been delayed by 1m-] times and the digital sine wave before being delayed are added, and among the n digital sine waves that have been added, the calculated sine wave is - Since either n digital sine waves are generated within a period or in periods different from each other, one ROM and one digital attenuator are required for each, regardless of the number of digital sine waves. , the scale of the enclosure configuration can be significantly reduced.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an example of a conventional multi-frequency digital sine wave generator, Fig. 2 is a block diagram showing an example of the present invention, and Fig. #13 is a block diagram for explaining the operation of the embodiment of the second WJ. This is a time chart. In the figure, 20 is a digital sine wave generator and 21 people. 21 B, S @, s li! switching li, 22
．． S@ is adder, 2 S, 24ktv jisfi, 25G
! ROM, 2@ is a digital attenuator, 21 is an attenuation amount setting section, 2I is an iterator, 32 is a signal generator for driving a switch,
33 and 34 are input terminals, and 35 is an output terminal. Figure 1

Claims (1)

[Claims] a digital sine wave generator that sequentially generates n digital sine waves with different frequencies within a predetermined period and repeatedly generates each period; a level adjuster for repeatedly adjusting the level of the waves to each of the periods;
means for sequentially overlaying the n digital sine waves level-adjusted by the level adjuster n-1 times and adding and outputting the respective oversized digital sine waves; A device for generating n digital positive square sine waves within the same period among one digital sine wave.