SU1388842A1 - Digital function generator - Google Patents

Abstract

The invention relates to automation and computer technology and can be used to provide metrological support for geophysical information and measurement systems that implement harmonic electromagnetic methods for prospecting and exploration of mineral deposits. The purpose of the invention is to enhance the functionality by simplifying the re-tuning of the phases and amplitudes of the output signals. The digital function generator consists of a clock pulse generator, a frequency divider, four address counters, a binary-to-RS converter, a two phase formers, three counting triggers, three delay elements, a first switch, a component storage unit, a multiplier, a second switch and five registers. The goal is achieved by introducing a binary code converter into a positional, KB trigger, three counting triggers, two phase formers, a storage unit for multipliers, three delay elements, and four registers. The generator generates three digital sinusoids at its outputs, it allows you to adjust the amplitudes and phases of the generated signals from the control panel, thereby significantly increasing the performance of tuning and calibrating geophysical information-measuring systems. 2 Il. S (l

Description

The invention relates to automation and computer technology and can be used in metro systems to provide logical measurements of the parameters of signals recorded during the search and exploration of mineral deposits by harmonic electromagnetic methods. In addition, it can be used for

setting up and calibrating equipment for detecting corrosion sites in underground

pipelines.

The purpose of the invention is to enhance the functionality by simplifying the resetting of the phases and amplitudes of the exhaust signals.

Figure 1 shows the structural scheme of the proposed digital generator; in fig. 2 - an example of the implementation of the phase shaper

The device consists of 1 clock pulse generator, 2 clock divider, first, second, third and fourth address counters 3-6 ,, a binary code to position converter 7, an FS-flip-flop 8, first and second shapers of phases 9 and 10, the first, the second and third counting triggers 11-13, the second 14, the first 15 and the third 16 delay elements, the first switch 17, the signal component storage unit 18, the storage unit 19 of multiplier coefficients 20, the second switch 21, the first 22, fourth 23 24, second, second 25 and third 26 D strov.

Inputs 27 and 28, respectively, the stop (STOP) and hare (START) inputs of the generator, and the outputs 29-31, respectively, the first, second and third digital codes. The outputs 32 and 33, respectively, are the first and second inputs of the imager of 9 phases, the output 34 is its output. The shaper of 9 and 10 phases consists of a USh 35 element, a frequency divider 36, a counting trigger 37, and an I 38 element.

As switches 17 and 21, a multiplexer and a demultiplexer can be used.

Digital function generator works as follows.

The device generates three digital sine waves of the same frequency, but with pc1 different adjustable amplitudes and phases. And the plots are regulated by Yu

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5 30

Q

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The variation of the coefficients recorded in the storage device 19 is controlled, and the required value of the phases is determined by the conversion factors of the counters contained in the formers 9 and 10 phases (Fig. -2). The values of the coefficients are set from the control panel (not shown).

Generator 1 generates a periodic pulse sequence, which is fed to the input of divider 2 frequency. Counter 3 contains 2 outputs and produces a binary output; the address code for the first switch 17, block 19, second switch 21. Address counters 4-6 generate 2 addresses and contain the CR rerout code. Each switch channel contains p + 1 inputs, and the higher-level input of each channel is used to set the sign sine wave The switchboard also contains p outputs for block 18 and (p +) - th for transmission sign from the output of counters 4-6 to the outputs of the device. In block 18, the order of addresses increases from 0 .. .0 to 1 1 ... 1, 2 values of the sinusoid in the range from O to 180 with a step of 80V2

The required discreteness of the value of the sinusoidal signal is provided by the appropriate choice of the number of bits n of the block 18. In block 19 there are 3 cells in which the coefficients are recorded, to which the corresponding digital sinusoids are multiplied. The required discreteness of adjustment of the sinusoidal signal is ensured by the choice of the number of bits of one cell, in FIG. 1, this number is equal to n.

The proposed generator can be in two modes: Stop and Start. In the Stop mode, at the input 27., The potential of the logical unit is fed, and at the input 38, the logic zero. In the Starting mode, the potentials at the inputs 27 and 28 are reversed. In the Stop Trigger mode; p 8 is transferred to the state of a logical unit and the positive potential resulting from its output nullifies divider 2, a counter: and 3-6, drivers of 9 and 10 phases, triggers 11-13, and registers 22-26 The listed circuit elements are in the zero state until the potentials change at the inputs 27 and 28. At the moment of switching the potentials at the output of the trigger

The potential of a logic zero appears, as a result of which the blocking on the inputs of the installation to zero of the j 8 divider 2, counters 3-6, formers 9-10, triggers 11-13, registers 22-26 is released.

The pulse sequence with the frequency fp, coming from the output 10 of the generator 1 to the input of the divider 2, is converted into a sequence of pulses with the frequency Go (K is the division factor of the frequency of the divider 2). Under the influence of each pulse from t5 of divider 2 output on digital outputs of counter 3, afsr changes to control switches 17 and 21. The binary code of the address from the output of counter 3 is converted into position converter 7, the outputs of which are sequentially made. Positive pulses to control the operation of counters 4-6, and before turning on the Start button, the potential of a logical unit is present on the 25th first output of the converter, and the logical zero on the second and third output. The pulses from the first output of the converter 7 are fed to the clock AOR input of the address counter 7 directly, as a result of which the output of the last is a change of addresses to form the first sinus

Soids and in the fifth register 24 are the values of the third sinusoid. The issuance of sinusoid codes occurs at the moment when the code of the first sinusoid appears, i.e. under the action of the next pulse from the first output of the converter 7.

The delay elements 14-16 are introduced to compensate for the propagation delay in the counters 4-6, the commutator, the tator 17, the storage devices, 18 and 19, the multiplier 20 and the commutator. At the moment of changing the sign of each of the sinusoids, overflow outputs of the counters 4-6 appear positive impulses under the action of which at the outputs of the flip-flops 11-13 appear the potentials of the logical unit, which flow through the switches 17 and 21 to the outputs of the device and serve to determine the sign sinusoids (the potential of a logical zero at the outputs of the flip-flops 11–13 denotes a negative value of the sinusoid, and the logical unit denotes a wave),

Thus, for two cycles of exchanging addresses at the outputs of each of the counters 4-6, the generator generates codes of three sinusoidal signals in the range from 0 to 360. This process is continuously repeated until the generator is stopped by the Stop signal.

To change the phase shift between

positive half days immediately after pressing the Start button, with sinusoids or their amplitude values of SRI A, it is necessary to press the Stop button,

and the pulses from the second and third inputs of the converter 7 arrive at the clock inputs of the address counters 5 and 6 after some time intervals equal to the phase shifts of the second and third sinusoids. The phase shifts are determined by the formers 9 and 10,

Synchronously with the formation of the next address at the outputs, 1 counters 4-6 open. the corresponding channels of the switch 17 and, at the output of block 18, the corresponding codes of the generated sinusoids are generated, which are sequentially multiplied by the multiplier 20 by the corresponding constant coefficients recorded for the three sinusoids in block 19,

Simultaneously with the appearance of the sinusoid codes, the outputs of the multiplier 20 open the channels of the switch 21 and j in the first register 22 the values of the first sinusoid are recorded, and in the fourth register 23 the values of the second

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From the control panel, you need to dial the required Cf and A values and when you press the Start button, the described process will be repeated.

In Stop mode, the inputs of the divider 36 and trigger 37 receive the potential of a logical unit, which resets the specified divider and trigger to zero and blocks them at the clock input. When the proposed generator is turned on in the Start mode, the blocker is removed from the divider 36 and the trigger 37. As a result, at the output of the divider 36, under the action of clock pulses from the second output of the converter 7 (Fig. 1), a positive potential appears at a time interval equal to the phase shift, which arrives at the counting input of the trigger 37 and translates it into a single state. The potential generated at the trigger 37 output is zeroed and the counter 36 is blocked and permission is given for

Soids and in the fifth register 24 are the values of the third sinusoid. The issuance of sinusoid codes occurs at the moment when the code of the first sinusoid appears, i.e. under the action of the next pulse from the first output of the converter 7.

The delay elements 14-16 are introduced to compensate for the propagation delay in the counters 4-6, the commutator, the tator 17, the storage devices, 18 and 19, the multiplier 20 and the commutator. At the moment of changing the sign of each of the sinusoids, overflow outputs of the counters 4-6 appear positive impulses under the action of which at the outputs of the flip-flops 11-13 appear the potentials of the logical unit, which flow through the switches 17 and 21 to the outputs of the device and serve to determine the sign sinusoids (the potential of a logical zero at the outputs of the flip-flops 11–13 denotes a negative value of the sinusoid, and the logical unit denotes a wave),

Thus, for two cycles of exchanging addresses at the outputs of each of the counters 4-6, the generator generates codes of three sinusoidal signals in the range from 0 to 360. This process is continuously repeated until the generator is stopped by the Stop signal.

To change the phase shift between

positive half0

five

0

five

From the control panel, you need to dial the required Cf and A values and when you press the Start button, the described process will be repeated.

In Stop mode, the inputs of the divider 36 and trigger 37 receive the potential of a logical unit, which resets the specified divider and trigger to zero and blocks them at the clock input. When the proposed generator is turned on in the Start mode, the blocker is removed from the divider 36 and the trigger 37. As a result, at the output of the divider 36, under the action of clock pulses from the second output of the converter 7 (Fig. 1), a positive potential appears at a time interval equal to the phase shift, which arrives at the counting input of the trigger 37 and translates it into a single state. The potential generated at the trigger 37 output is zeroed and the counter 36 is blocked and permission is given for

passing through the element 38 clock pulses from 32 to the output 34 of the phase shaper.

Thus, the proposed generator generates three digital sinusoids with adjustable amplitudes and phases. Because it is not necessary to change the phase. reprogramming the permanent storage devices (as provided in the prototype), it is enough to change only the frequency ratio of the divider 36 (FIG. 2), thus, the generator setting for the specified phase shift is simplified. Independent adjustment of the amplitudes of sinusoids Implementing is the pre-recording in the storage unit of the required values of the kO effects,

Claims (1)

Invention Formula A digital function generator containing a clock pulse generator, a frequency divider, four address counters, two switches, a storage unit for signal components and a first register, and the output of the clock generator is connected to the count input of a frequency divider, the output of which is connected to the counting the input of the first address counter, the outputs of the second, third and fourth address counters are connected respectively to the first, second and third information inputs of the first switch; the output of which is connected to the address To the input of the signal storage unit, the second information output of the second switch is connected to the data input of the first register, the output of which is connected to the first OUTPUT of the generator, characterized in that, in order to extend the functionality by simplifying the resetting of the phases and the amplitudes of the extracted signals , a binary code to positional converter, an RS trigger, three counting flip-flops;, two phase formers, a coefficient value storage unit, a multiplier, three delay elements, four registers, Rich osta.nova oscillator input is connected to the S-input of RS-trigger and to the R-input of which is connected to the input for starting the generator, RS-flip-flop output is connected to the reset inputs of the frequency divider, the first, second, third and the fourth address counters, the first, second and third counting triggers, the first, second, third from the first, fourth and fifth registers, the first inputs of the first and second phase formers, the output of the first address counter is connected to the input of the binary code converter 10, control input of the first and second switches and the address input of the storage unit of the coefficient values, the first output of the binary-to-position converters 15 is connected to the counting input of the second address counter and, through the first delay element, to the clock inputs of the first, second and third registers, the second output of the converter 20 binary code to positioner is connected to the second input of the first phase shaper, the output of which is connected to the counting input of the third address counter and through the second 25 delay element - to the synchronization input of the fourth register, the third output of the binary to positional transducers is connected to the second input of the second driver 30 phases, the output of which is connected to the counting input of the fourth address counter and, via the third delay element, to the synchronization input of the fifth register, the overflow outputs of the second, third and fourth address counters are connected respectively to the counting inputs of the first, second and third counting triggers, the outputs of which connected to senior inputs 4Q bits of the first, second and third information inputs of the first switch, the outputs of the storage unit of the signal components and the storage unit of the coefficient values are connected to g5 to the first and second information inputs of the multiplier, the output of which is connected to the information input of the second switch, the input of the higher bit of which is connected to the output - the high order of the output of the first switch, the second and third outputs of the second switch are connected to the data inputs of the fourth and nth registers, respectively the outputs of the fourth and fifth registers are connected to the input data of the second and third registers, respectively, the outputs of the second and third registers are connected to the second and third outputs of the generator a. 35 50 55 J  WITH 39 J with with 3 Ultrasound PG 15 -I 37 (D / V.2