KR100194918B1 - Tone generator - Google Patents

Abstract

In the tone generating device, it is difficult to integrate when using DSP for tone generation, and it is difficult to integrate when there are many tone sources even when using logic circuit, and the tone source should be changed whenever the tone specification is changed.

To this end, the jump data set to different values corresponding to each of the plurality of tones and the first and second frequencies of the tones and the previous tone address for the corresponding tones are output by predetermined timing control. The jump data and tone address pairs are sequentially selected in correspondence with the timeslots assigned to each tone, and the tone addresses are determined according to the selected tone addresses and jump data. Outputs tone data of a storage area corresponding to the tone address among tone data having a plurality of sample values PCM-converted for one frequency waveform, and synthesizes each tone data for the first and second frequencies. Generates a tone.

Therefore, it is easy to integrate by minimizing the memory capacity for storing tone data, and the tone source does not need to be changed even if the tone specification is changed.

Description

Tone generator

1 is a block diagram of a conventional tone generating device.

2 is a block diagram of a tone generating device according to the present invention.

3 is a detailed block diagram of the first address storage unit 10 of FIG.

4 is an operating waveform diagram of each part of FIG. 2 and FIG.

5 is an explanatory diagram of tone data generation of the present invention.

* Explanation of symbols for main parts of the drawings

10-14: 1st-Nth ADDRESS STORAGE 16

18: address determination unit 20: ROM

22: linear conversion unit 24: latch unit

26: synthesis unit 28: PCM conversion unit

30: output control unit 32: timing control unit

34,38: First and second jump registers 36,40: First and second address registers

42: frequency selector

The present invention relates to a tone generator, and more particularly, to a tone generator for generating various tones using only one tone source.

In general, the exchange system includes a tone generator, and generates various tones such as dial tone, busy tone, ring back tone, and the like, and supplies them to subscribers as needed. For this purpose, any one of the stream highways is used for channel allocation for tone generation, and a unique fixed time slot corresponding to each tone is always outputted. For example, dialtone is assigned to timeslot 0, busytone is assigned to timeslot 1 and ringbacktone is assigned to timeslot 2 so that the corresponding timeslot is connected to the subscriber's call channel as needed. . The various tones typically use a dual tone in which two different frequency signals are synthesized. For example, in the case of a dial tone, a frequency signal of 340 kHz and 440 kHz is synthesized.

As one of the techniques for generating the tones as described above, a technique for generating a tone by software using a digital signal processor (DSP) has been used. However, when the DSP is used, cores must be integrated together when the ASIC is used, and thus the price cannot be realized as a gate array.

Accordingly, a tone has been generated using a logic circuit composed of an address counter 2 and a ROM 4 as shown in FIG. In FIG. 1, the ROM 4 stores all tone data corresponding to various tones, that is, tone data for each tone. In this case, the tone data is typically data sampled at 8 mu s. In this state, the address counter 2 counts 8 ms of sampling clock, generates a tone address which is cyclically repeated, and applies it to the ROM 4. The ROM 4 then outputs the tone data stored in the memory area corresponding to the tone address to the corresponding timeslot in 8-second periods. Here, the ROM 4 occupies as many memory regions as the tone source increases as all the tone sources are stored as described above. For example, even one dial tone as described above occupies a memory area of about 400 bytes. This increases the price and makes it difficult to ASIC by having to use larger ROMs. In addition, because the tone source for each tone is fixed, considering that the specifications of the tones vary from country to country, the tone source must be changed according to each country.

As described above, in the case of using a DSP for tone generation, integration is difficult and the price is increased, and even in the case of using a logic circuit, when the tone source is large, integration is difficult as the size of the ROM increases and the price is increased. There was a problem. In addition, when using a logic circuit, there is a problem that the tone source must be changed whenever the tone specification is changed.

It is therefore an object of the present invention to provide a tone generating apparatus which can solve the above problems.

Another object of the present invention is to provide a tone generating apparatus capable of generating various tones using only one tone source.

It is still another object of the present invention to provide a tone generating apparatus that can be easily integrated and reduce the cost by using only one tone source.

Still another object of the present invention is to provide a tone generating apparatus capable of generating various tones without changing the tone source even if the specifications of the tones vary.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram of a tone generating apparatus according to the present invention, wherein a plurality of tones and jump data set to different values corresponding to respective first and second frequencies of the tones and the previous tones for the corresponding tones are shown. A first to Nth address storage unit 10-14 which stores an address and outputs jump data and tone addresses for each tone by predetermined timing control, and is allocated to each tone by predetermined timing control. A tone selector 16 that sequentially selects each of the jump data and the tone address pair corresponding to the timeslot, and a tone address determiner that determines and outputs the tone address according to the selected tone address and the jump data. 18) and tone data having a plurality of PCM-converted sample values for one frequency waveform and outputting tone data of a storage area corresponding to the tone address. 20, a linear converter 22 for linearly converting the output tone data, a latch 24 for latching the output of the linear converter 22, and an output of the linear converter 22 And an adder 26 for adding the latched data to the latch section 24, a PCM converter 28 for PCM converting the added data, and an output of the PCM converter 28 for the timing control means. The output control unit 30 outputs the tone stream highway only for a predetermined period by the control of the control unit, the first-Nth address storage unit 10-14, the tone selector 16, the latch unit 24, and the output unit. The timing control unit 32 performs timing control on the control unit 30.

3 is a detailed block diagram of the first address storage unit 10 of the second diagram. First and second jump data set to different values corresponding to different first and second frequencies for one tone are shown in FIG. The first and second jump registers 34 and 38 storing the first and second address registers respectively storing first and second tone addresses of the first and second frequencies as first and second tone addresses, respectively. The first jump data and the first tone address are selectively outputted during the first half period in the corresponding time slots by the registers 36 and 40 and the timing control of the timing controller 32, and the second jump data and the second jump data during the next half period. And a frequency selector 42 for selectively outputting the second tone address.

4 is an operational waveform diagram of each part of FIGS. 2 and 3.

5 is an explanatory diagram of tone data generation of the present invention.

An operation example of FIGS. 2 and 3 according to the present invention will be described in detail with reference to the operation waveform diagram of FIG.

First, according to the present invention, the first and second jump registers 34 as shown in FIG. 3 for storing the first and second frequency-specific jump data and tone addresses for one tone in the 256-byte ROM 20 of FIG. 36) and two first and second address registers 36 and 40 are required. If the number of tone sources is N, there are N corresponding address storage portions, and thus, the tone selection unit 16 is controlled.

In addition, in order to generate a tone, first, an 8-bit nonlinear PCM data stored in the ROM 20 is read out before a time slot of 8 ms. At this time, the first frequency value during the half period of the corresponding timeslot is stored in the first address register 36, and is then converted into PCM data again during the next time slot half period to output tone data. In this case, as the tone sources increase, only the address storing unit as shown in FIG. 3 increases by the corresponding tone source, and the logic for adding the two frequencies can be used without increasing the logic in common.

In addition, the timing controller 32 is always output based on the frame synchronizing signal FS as shown in FIG. 4a, which is a network synchronizer signal of the exchange, so that timing distribution and control as shown in FIG.

4 shows an example of four ton sources. That is, assuming that four different tones in four consecutive time slots are output, two selection signals SEL2 of the tone selector 16 are required, that is, SEL21 and SEL22. The first jump register 34 and the first address register 36 generate one frequency, and the second jump register 38 and the second address register 40 generate another frequency. The selector 42 selects S_CLKOO once, and selects two frequencies for each half period of one time slot. The address determining unit 18, which is composed of an adder, generates a tone address so that each sample value of a quarter period is selected for the 256-byte tone data stored in the ROM 20. This will be described in more detail as follows. First, 256 samples of 1/4 cycles are stored for one frequency waveform, and then output symmetrically. Here, 256 samples change depending on the frequency value and the jump value. The corresponding values at the time of storing and reading the tone data are shown in FIG.

That is, once the phase output by the selected frequency is the P II region, the address determination unit 18 may subtract 255 and take a 1's complement. If the address should be mapped to the P III area, subtract 511 and change only the sign.

In addition, since the tone data read from the ROM 20 cannot be synthesized as it is, the linear conversion unit 20 first converts the linear data into a linear structure, and then stores the data in the latch unit 24 first, and then in the next frequency value and the adder 26. Add. The tone data added as described above and synthesized into dual tones is converted into PCM data by the PCM conversion unit 28 and outputted.

In the meantime, the tone data is created and stored in the ROM 20 in advance as an example.

First, set π, which is half period, to 32768. If the sampling frequency is 8 는다, set the same position to make the data output once per period. In this case, based on having 256 samples within a quarter period, each sample value is determined by the following Equation (1), and has a phase step θ as shown in the following Equation (2).

When each sample value is calculated | required by said Formula (1)-(2), it becomes like following Table 1.

Therefore, 256 sample values as shown in Table 1 are stored in the ROM 20 as tone data. So, for example, if you want to generate tone of 340㎐, jump data is set as follows. First, the jump value is as shown in Equation 3 below.

Accordingly, when the jump data is set to 43 based on the above three equations, the ROM 20 outputs the 0 th sample value → 43 th sample value → 86 th sample value →,.

As described above, the present invention is a logic circuit using only one tone source, and generates various tones, thereby minimizing memory capacity for storing tone data, making it easy to integrate and reducing costs, and even changing specifications of tones. There is an advantage to not having to change the tone source.

Claims (7)

In the tone generating apparatus, a plurality of tones and jump data set to different values corresponding to each of the first and second frequencies of the tones and the previous tone address for the corresponding tone are stored, and are stored in a predetermined timing control. A plurality of address storage means for outputting jump data and tone addresses for each tone by means of a predetermined timing control, and the jump data and tone address pairs are sequentially selected corresponding to the time slots assigned to each tone by a predetermined timing control. Storing tone data having a plurality of sample values that are PCM-converted for one frequency waveform, and storing the tone address determining means for determining and outputting the tone address according to the selected tone addresses and jump data. Tone data storage means for outputting tone data of a storage area corresponding to the tone address; Tone generation comprising: synthesizing means for synthesizing tone data output for each of two frequencies to generate dual tones, and timing control means for timing control of the address storing means, tone selection means, and synthesizing means; Device. The apparatus of claim 1, further comprising: first and second jumps storing first and second jump data set to different values corresponding to different first and second frequencies of the tone corresponding to the address storing means. Registers, first and second address registers for storing the tone addresses immediately before the first and second frequencies as first and second tone addresses, respectively, and corresponding tones by timing control of the timing control means. And a frequency selecting means for selectively outputting the first jump data and the first tone address during the first half period in the timeslot of the second slot, and selectively outputting the second jump data and the second tone address during the next half period. Device. The linear conversion unit 22 according to claim 2, wherein the synthesizing means linearly converts the output tone data, a latch unit 24 for latching the output of the linear conversion unit 22, and the linear conversion unit. And an adder (26) for adding the output of (22) and data latched to the latch section (24), and a PCM converter (28) for PCM converting the added data. 4. The tone generating apparatus according to claim 3, further comprising an output controller (30) for outputting the output of the PCM converter (28) to the tone stream highway only for a predetermined period by the control of the timing control means. . A tone generating apparatus comprising: first and second jump registers storing first and second jump data set to different values corresponding to different first and second frequencies for a tone, and the first The first and second address registers for storing the tone address immediately before the second frequency as the first and second tone addresses, respectively, and during the first half period in the corresponding timeslot by timing control of the timing control means. A frequency selecting means for selectively outputting the first jump data and the first tone address and selectively outputting the second jump data and the second tone address during the next half period, and a tone address according to the selected tone addresses and jump data. A tone address determining means for determining and outputting the tone address; and tone data having a plurality of sample values PCM-converted for one frequency waveform. A tone data storage means for outputting tone data of a storage area corresponding to the frequency difference; synthesizing means for synthesizing the tone data output for each of the first and second frequencies to generate dual tones; And a timing control means for timing control on the synthesizing means. The linear conversion unit 22 according to claim 5, wherein the synthesizing means linearly converts the output tone data, a latch unit 24 for latching the output of the linear conversion unit 22, and the linear conversion unit. And an adder (26) for adding the output of (22) and data latched to the latch section (24), and a PCM converter (28) for PCM converting the added data. 7. The tone generating apparatus as claimed in claim 6, further comprising an output controller (30) for outputting the output of the PCM converter (28) to the tone stream highway only for a predetermined period by the control of the timing control means. .