JPH0310262B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal processing device that converts the rate of multiplexed PCM signals. First, as shown in Figure 1, a conventional digital signal processing device includes a sampling circuit 1 that obtains a PAM signal that takes values discretely on the time axis from a time-continuous analog input signal, and a sampling circuit 1 that obtains a PAM signal that takes values discretely on the time axis from a time-continuous analog input signal, and a sampling circuit 1 that generates a PAM signal that takes values discretely on the time axis. a quantization circuit 2 that converts into a discrete digital signal (binary code sequence), a digital filter 3 that performs digital signal processing and shapes it into a desired spectrum, and a D/A conversion that converts this output into an analog sample value. circuit 4
and an interpolation circuit 5 that interpolates this output to obtain a desired analog signal. When an acyclic digital filter, which is a digitized version of a well-known transversal filter, is used for spectrum shaping in the digital filter 3, its input signal x (nT ₁ ) and output signal y (nT ₁ ) at time nT ₁ (both The input/output relationship of the digital value is as follows: y(nT ₁ )= _M 〓 ^K=0 a _k x [(n−k)T ₁ ] (1). However, n and M are positive integers, T ₁ is a sampling period, and a _k is a constant. There are three types of operations included in equation (1): addition, multiplication, and unit time delay, and equation (1) can be performed with the configuration shown in FIG. In the same figure, 211 to 21M are T ₁ time delay circuits, 220, 221, ... 22M-1, 22M are multipliers with constants a ₀ , a ₁ ..., a _M-1 , a _M , and 23 is an adder. It is. Next, a rate conversion acyclic digital filter that can be used as the digital filter 3 in FIG. 1 will be explained. For simplicity, 2
The case where the sampling rate is doubled will be explained. The input to this filter is shown in Figure 3a.
Sample values (digital values) arriving at a rate of sampling frequency _s (1/T ₁ ) as shown in
If this is _the case, zero data is interpolated as shown in _FIG . Here, T ₂ =1/2 _s . Now, if the input/output relationship of this digital filter is y(nT ₂ )= _M 〓 ^K=0 a _k x [(n-k)T ₂ ]...(2), then the sample value ( When the actual data) is applied to the input terminal, the term x [(n-k)T ₂ ] of odd order k becomes zero, and in reality, only the term of even order k is calculated, while During interpolation using data, if only the terms of odd order k are calculated, the output signal y(nT ₂ ) is obtained. Therefore, the rate conversion acyclic digital filter is equivalently represented by a parallel filter shown in FIG. This rate conversion acyclic digital filter is
2T ₂ time delay circuit 311~31m, multiplier 321
~32m, an even-order filter consisting of an adder 35, a _T2 time delay circuit 330, _{a 2T2} time delay circuit 3
31 to 33m, multipliers 341 to 34m, adder 3
6 odd-numbered filters, and a switch 3
7 at the _2S rate and alternately outputs the calculation results of the even-order filter and the odd-order filter, thereby obtaining a desired output signal y(nT ₂ ) at the _2S rate. However, M = 2m. A rate conversion acyclic digital filter in which an even-order filter and an odd-order filter are implemented using separate hardware can be configured as shown in FIG. 5, and its time sequence is as shown in FIG. 6. . In FIG. 5, an input signal x(nT ₂ ) is input to an even-order filter 51 and an odd-order filter 52, and their respective outputs are input to a multiplexer 53 to obtain an output signal y(nT ₂ ) at its output.
The timing control circuit 54 controls the timing of the even-order filter 51 and the odd-order filter 52. As shown in FIG. 6, for example, the input signal x
The even-order operation 61 and the odd-order operation 62 regarding (nT ₁ ) are the even-order output 66 for the output signal y(nT ₂ ).
and is output as an odd-order output 67. The same applies to the even-order operation 63 and the odd-order operation 64 regarding the input signal x [(n+1)T ₁ ].
5 and 68 indicate the odd-order output and the even-order output in the output signal y(nT ₂ ), respectively. Now, the rate-switching acyclic digital filter that has been described so far accepts one channel of input signal, but if the input signal of multiple channels is to be converted, for example, by a factor of two, the conventional rate-switching acyclic digital filter is
It has the disadvantage that it requires hardware that is twice the number of channels as the number of channels. SUMMARY OF THE INVENTION An object of the present invention is to provide a digital signal processing device that can realize rate exchange of time-division multiplexed input signals of a plurality of channels with simple hardware. The digital signal processing device of the present invention has a memory that stores PCM signals of N channels (N is a natural number) that are time-division multiplexed and transmitted at one sample period for each channel. a digital filter obtained by dividing an m-th order (m is a natural number) acyclic digital filter into N parts; and a first switching circuit that selects the output of the storage circuit as one of the inputs of the N digital filters. , a second switching circuit that switches the outputs of the N digital filters, and the i-th (i=0, 1,
The digital filter of
It has a function of executing product-sum with the PCM signal input +i before, and calculates the PCM signal of each channel input one sample before during the time interval in which each PCM signal is input. The first switching circuit switches the PCM signals so that one digital filter corresponds to the PCM signal of each channel, and inputs the PCM signals to each digital filter. During signal input intervals, the input digital filters of the PCM signals of each channel are advanced one by one, and the i
PCM that performed the th digital filter input
The signal is input to the i+1th digital filter, the PCM signal input to the last digital filter is inputted to the 0th digital filter, and the second switching circuit changes the output of each digital filter at a timing synchronized with the first switching circuit. The present invention is characterized in that by switching output and obtaining N outputs at intervals of inputting a PCM signal of one channel, an N-times rate conversion digital filter operation is performed on the PCM signal. FIG. 7 is a block diagram showing one embodiment of the present invention;
FIG. 8 is a timing diagram showing the operation of FIG. 7. The time-division multiplexed input signal of 2 channels (ch) is inputted alternately as 1ch and 2ch, so
These are switched by the selector 70 and written into the respective memories 71 and 72. At the next timing (between times t ₂ and t ₃ ) after the timing when the ch ₁ data was written (between times t ₁ and t ₂ ), the written ch ₁ data is transferred to the even-order film 7 via the selector 73.
4 and get its output. At the same time,
The ch ₂ data written before time t ₁ is sent to the odd-order filter 75 via the selector 73, and its calculation output is obtained. Then, the outputs of the odd-order filter 74 and the even-order filter 75 are further time-divided and outputted by the selector 76 at the next timing (between times _t3 and _t4 ), time _t34 . The data of 2ch is written to the memory 72 via the selector 70 and updated at the timing between times t ₂ and t ₃ . Selector 73 at time t ₃
and pass the ch1 data to the odd-order filter 75.
, send the data of ch ₂ to the even-order filter 74,
Get that output. The selector 76 is switched at time _t45 , and the outputs of the even-order filter 74 and the odd-order filter 75 are time-divided and output. Repeat this operation. A similar principle can be used to convert an N-channel time-division multiplexed input signal to a sampling rate N times higher, as described below. The conventional rate conversion acyclic digital filter that performs N-times rate conversion for a single input is described in the ninth section.
As shown in the figure. The number of interpolations for zero data is N-1, and when actual data enters, the 0th and Nth
The calculation is performed only on the 2Nth data, and at the next timing, the calculation is performed only on the 1st, N+1st, etc. data. Below, filters (l=0, 1...
..., 0iN-1) as the i-th filter, after the actual data is input, the 0th-order filter 920, the 1st-order filter 921..., the i-th filter
Next filter 92i...n-1st filter 92n
By sequentially inputting and outputting the output of -1 through selectors 93 and 94, an output signal whose rate has been converted by N times is obtained. Note that 91 is a memory. By multiplexing these filters, it is possible to convert the rate of N _channels of time-division multiplexed input signals. FIG. 10 is a block diagram of a rate conversion acyclic digital filter in this case as a second embodiment of the present invention, and FIG. 11 is a timing diagram showing its operation. Since time-division multiplexed input signals of N channels (ch) are inputted in the order of 1ch, 2ch, . . . , Nch, these are written into the respective memories 101 to 10N for each channel. ch ₁
The timing at which data was written (time t ₁ ′~
At the next timing (between times t _{2 ′} and t ₃ ′), this written ch ₁ data is transferred to the selector 120.
is sent to the 0th order filter 130 via
chN written before t ₁ ′, ..., chi, ..., ch ₂
are passed through the selector 120 to the first filter 131, .
31 to 13 N-1 ) to obtain the calculation output. Then, the selector 140 is switched at intervals of 1/N of the sampling rate, and the calculation outputs of the 0th to N-1st filters are time-divided and output. Same timing (between time t ₂ ′ and t ₃ ′)
The 2ch data is written to the memory 102 and updated. At time _t3 ', selector 120 is switched, data of ch ₁ is sent to primary filter 131, and similarly
The data of chN, ..., chi, ..., ch ₂ is passed through the selector 120 to the second filter 13, respectively.
2,..., N-i ₊ 2nd order filter 13 N-i ₊₂ ,...
..., is sent to the 0th order filter 130, and its calculation output is obtained. And 1/N of the sampling rate
The calculation outputs of the first to N-1st and 0th order filters are time-divided and outputted by switching with the selector 140 at intervals of . The same procedure is repeated sequentially. Thus, according to the present invention, time division multiplexing of fractional channels can be performed using the minimum necessary hardware.
Rate conversion digital filtering for PCM signals can be realized.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a general digital signal processing device, Fig. 2 is a block diagram showing a well-known acyclic digital filter used in a conventional digital signal processing device, and Fig. 3 a and b are PCM signal rates. Explanatory diagrams illustrating the well-known concept of conversion, Figures 4 and 5
The figure is a block diagram showing a well-known rate conversion acyclic digital filter that performs double rate conversion for a single input, Figure 6 is a timing diagram showing the operation of Figure 5, and Figure 7 is for a two-channel input. FIG. 8 is a timing diagram showing the operation of FIG. 7, and FIG. 9 is a single input FIG. 10 is a block diagram showing a well-known rate conversion acyclic digital filter that performs n-fold rate conversion on N-channel inputs. FIG. 11 is a block diagram showing the conversion acyclic digital filter, and FIG. 11 is a timing diagram showing the operation of FIG. 1... Sampling circuit, 2... Quantization circuit, 3...
Digital filter, 4...D/A conversion circuit, 5
...Interpolation circuit, 70, 73, 76, 120, 14
0...Selector, 71, 72, 101, 102,
..., 10N...Memory, 74...Even number order filter, 75...Odd number order filter, 130, 131,
...13 N-1 ... 0th order, 1st order, ..., N-1
Next filter.

Claims (1)

[Claims] 1 A memory circuit that stores PCM signals of N channels (N is a natural number) that are time-division multiplexed and transmitted for one sample period for each channel, and an m-th order (m is a natural number) acyclic digital filter. a first switching circuit that selects the output of the storage circuit as one of the inputs of the N digital filters, and a second switching circuit that switches the outputs of the N digital filters. The i-th (i=0, 1, 2, . . . ) digital filter among the N digital filters is lN+i (<m)-th (l=
0, 1, 2, ...) and the PCM signal input before lN+i.
The PCM signal of each channel inputted before sampling is output from the storage circuit at a time interval N times the time interval, and the first switching circuit outputs the PCM signal of each channel.
Switch the PCM signal so that one digital filter corresponds to it and input it to each digital filter, and at the interval when the next PCM signal is input, the digital filter to which the PCM signal of each channel is input is advanced one by one. , the PCM signal input to the i-th digital filter is the i-th +1
The PCM signal inputted to the 0th digital filter and inputted to the last digital filter is inputted to the 0th digital filter, and the second switching circuit switches and outputs the output of each digital filter at a timing synchronized with the first switching circuit, A digital signal processing device characterized in that the PCM signal of one channel is subjected to an N-times rate conversion digital filter operation by obtaining N outputs at intervals of inputting the PCM signal of one channel.