JPS57143964A - Multifrequency signal receiver - Google Patents

Multifrequency signal receiver

Info

Publication number
JPS57143964A
JPS57143964A JP56030250A JP3025081A JPS57143964A JP S57143964 A JPS57143964 A JP S57143964A JP 56030250 A JP56030250 A JP 56030250A JP 3025081 A JP3025081 A JP 3025081A JP S57143964 A JPS57143964 A JP S57143964A
Authority
JP
Japan
Prior art keywords
adder
output
multiplier
multipliers
inputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56030250A
Other languages
Japanese (ja)
Inventor
Kensaku Fujii
Yasumasa Iwase
Yoshikatsu Shiraishi
Akira Fukui
Kazuto Hirose
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP56030250A priority Critical patent/JPS57143964A/en
Publication of JPS57143964A publication Critical patent/JPS57143964A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q1/00Details of selecting apparatus or arrangements
    • H04Q1/18Electrical details
    • H04Q1/30Signalling arrangements; Manipulation of signalling currents
    • H04Q1/44Signalling arrangements; Manipulation of signalling currents using alternate current
    • H04Q1/444Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies
    • H04Q1/45Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies using multi-frequency signalling
    • H04Q1/457Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies using multi-frequency signalling with conversion of multifrequency signals into digital signals
    • H04Q1/4575Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies using multi-frequency signalling with conversion of multifrequency signals into digital signals which are transmitted in digital form

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To decrease the number of multipliers of a linear cyclic digital filter without losing the advantage that a nucleus generating means is unnecessary, by applying high-speed Fourier transform algorithm for frequency thinning. CONSTITUTION:An input signal from a terminal 1 is multiplied at a multiplier 30 by a window function supplied from a window function generator 70. The output of the multiplier 30 is inputted to an adder 44 directly and through a shift register 52, and frequency-thinning high-speed Fourier transform algorithm is applied to the output of the multiplier 30. The output of the adder is supplied through a time slot conversion memory 57 to a linear cyclic digital filter consisting of a one-sampling-period delay register 56, one-word-length shift registers 53 and 54, multipliers 38 and 39, and adders 45 and 46, and the adder 45 generates a real part output and an imaginary part output alternately at intervals of one time slot. Both the outputs are squared by an adder 37 respectively, and the real number part is passed through a shift register 55 and then inputted to an adder 43 simultaneously with the imaginary number part, thereby detecting the presence of the input signal on the basis of the output of the adder.
JP56030250A 1981-03-03 1981-03-03 Multifrequency signal receiver Pending JPS57143964A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56030250A JPS57143964A (en) 1981-03-03 1981-03-03 Multifrequency signal receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56030250A JPS57143964A (en) 1981-03-03 1981-03-03 Multifrequency signal receiver

Publications (1)

Publication Number Publication Date
JPS57143964A true JPS57143964A (en) 1982-09-06

Family

ID=12298458

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56030250A Pending JPS57143964A (en) 1981-03-03 1981-03-03 Multifrequency signal receiver

Country Status (1)

Country Link
JP (1) JPS57143964A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0686338A (en) * 1991-12-31 1994-03-25 American Teleph & Telegr Co <Att> Method for detection of control signal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0686338A (en) * 1991-12-31 1994-03-25 American Teleph & Telegr Co <Att> Method for detection of control signal

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