JPS57143964A - Multifrequency signal receiver - Google Patents

Abstract

PURPOSE:To decrease the number of multipliers of a linear cyclic digital filter without losing the advantage that a nucleus generating means is unnecessary, by applying high-speed Fourier transform algorithm for frequency thinning. CONSTITUTION:An input signal from a terminal 1 is multiplied at a multiplier 30 by a window function supplied from a window function generator 70. The output of the multiplier 30 is inputted to an adder 44 directly and through a shift register 52, and frequency-thinning high-speed Fourier transform algorithm is applied to the output of the multiplier 30. The output of the adder is supplied through a time slot conversion memory 57 to a linear cyclic digital filter consisting of a one-sampling-period delay register 56, one-word-length shift registers 53 and 54, multipliers 38 and 39, and adders 45 and 46, and the adder 45 generates a real part output and an imaginary part output alternately at intervals of one time slot. Both the outputs are squared by an adder 37 respectively, and the real number part is passed through a shift register 55 and then inputted to an adder 43 simultaneously with the imaginary number part, thereby detecting the presence of the input signal on the basis of the output of the adder.