JPS5849023B2 - Manufacturing method for semiconductor devices - Google Patents

Manufacturing method for semiconductor devices

Info

Publication number
JPS5849023B2
JPS5849023B2 JP52137948A JP13794877A JPS5849023B2 JP S5849023 B2 JPS5849023 B2 JP S5849023B2 JP 52137948 A JP52137948 A JP 52137948A JP 13794877 A JP13794877 A JP 13794877A JP S5849023 B2 JPS5849023 B2 JP S5849023B2
Authority
JP
Japan
Prior art keywords
electrode
solder
film
semiconductor substrate
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52137948A
Other languages
Japanese (ja)
Other versions
JPS5471562A (en
Inventor
修六 桜田
裕二 新野
裕彦 池田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
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Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP52137948A priority Critical patent/JPS5849023B2/en
Publication of JPS5471562A publication Critical patent/JPS5471562A/en
Publication of JPS5849023B2 publication Critical patent/JPS5849023B2/en
Expired legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/01006—Carbon [C]
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    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01093—Neptunium [Np]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12036—PN diode

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置の製法に係り、金属蒸着膜から成る
電極をエッチング液から保護する方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for protecting an electrode made of a metal vapor deposited film from an etching solution.

一般に、半導体装置を組立てるにはＰＮ接合を有する半
導体基体の少なくとも１つの主表面にオーミツクコンタ
クト用、およびロウ材接着用の電極を真空蒸着法等で形
成し、この電極上にさらに軟質のロウ材を介して支持電
極を兼ねる放熱板等を接着し、半導体素子を得る。Generally, in order to assemble a semiconductor device, an electrode for ohmic contact and solder material adhesion is formed on at least one main surface of a semiconductor substrate having a PN junction using a vacuum evaporation method, and then a soft solder material is further applied on top of this electrode. A heat dissipating plate, which also serves as a support electrode, is bonded via the material to obtain a semiconductor element.

その後、半導体素子を所定のエッチング液に浸漬して化
学処理（アフタエツチ）を行ない、半導体基体周辺部の
破損や欠陥を除去し、素子の特性の回復をはかる手法が
とられている。Thereafter, the semiconductor element is immersed in a predetermined etching solution to perform a chemical treatment (after-etch) to remove damage and defects around the semiconductor substrate and restore the characteristics of the element.

第１図はこのような工程を経て作られたダイオードの一
例で、ＰＮ接合を有する半導体基体１４、基体１４の一
対の主表面に形成されたオーミツクコンタクト用の電極
膜１ ３ ，１５、電極膜１５の中央部および電極膜１
３の全面に形成された電極リード用ロウ材１６、放熱板
用ロウ材１２、放熱板１１、電極リード１７から成る。FIG. 1 shows an example of a diode made through such a process, which includes a semiconductor substrate 14 having a PN junction, electrode films 1 3 and 15 for ohmic contact formed on a pair of main surfaces of the substrate 14, and electrodes. Central part of membrane 15 and electrode membrane 1
The electrode lead brazing material 16, the heat dissipation plate brazing material 12, the heat dissipation plate 11, and the electrode lead 17 are formed on the entire surface of the electrode lead 3.

コンタクト用電極膜１３，１５としては、特にコンタク
ト抵抗の小さいＣｒまたはＡｅ膜を半導体基体１４に隣
接して形成し、さらにロウ材と密着性の良いＡｕｔＡｇ
ｔＮｉ等を積層させた構造が望ましい。As the contact electrode films 13 and 15, a Cr or Ae film having particularly low contact resistance is formed adjacent to the semiconductor substrate 14, and an AuAg film having good adhesion to the brazing material is formed.
A structure in which tNi or the like is laminated is desirable.

しかし、上記構造の半導体基体は、アフタエッチの際ニ
、エッチング液とコンタクト用電極膜トが化学反応を起
こし（活性を有し）、半導体基体とコンタクト用電極間
で剥離現象が生ずる。However, in the semiconductor substrate having the above structure, during after-etching, the etching solution and the contact electrode film undergo a chemical reaction (have activity), and a peeling phenomenon occurs between the semiconductor substrate and the contact electrode.

特に上記したオーミツクコンタクト用として良好なＣ
ｒ ｔ Ａｅはエッチング液と反応しやすい。Particularly good for the above-mentioned ohmic contacts.
r t Ae easily reacts with the etching solution.

この現象により半導体素子の特性劣化、特に電極部で部
分的に電流不通を生じたり、剥離した電極材料がＰＮ接
合露出部に付着することにより耐電圧が劣化したりする
難点が避けられなかった。This phenomenon inevitably leads to deterioration of the characteristics of the semiconductor element, especially partial current interruption at the electrode portion, and deterioration of withstand voltage due to peeled electrode material adhering to the exposed portion of the PN junction.

このコンタタト用電極膜剥離現象は、次のメカニズムで
進行する。This contact electrode film peeling phenomenon progresses by the following mechanism.

真空蒸着法により形成されたコンタクト電極膜には肉眼
では判別できない小さなピンホールがあり、このビンホ
ールよりエッチング液が浸透し、Ｓｉ一第一層金属部分
で反応する。The contact electrode film formed by vacuum evaporation has small pinholes that cannot be seen with the naked eye, and the etching solution permeates through these pinholes and reacts with the Si-first metal layer.

電極膜金属をＣｒ、エッチング液をＮａＯＨ：水溶液と
すれば、Ｃ ｒ −ＮａＯＨ 間ではＣｒ０３＋２Ｎａ
ＯＨ−＋２Ｎａ＋Ｃｒ０４” ＋Ｈ２０の反応式に示さ
れる様な反応が起る。If the electrode film metal is Cr and the etching solution is a NaOH:aqueous solution, Cr03+2Na is formed between Cr and NaOH.
A reaction occurs as shown in the reaction formula: OH-+2Na+Cr04''+H20.

このとき、Ｃ ｒ ０ ３は、蒸着時の稀少残留酸素と
Ｃｒが反応したり、蒸着後の熱処理（シンターリング）
時Ｓｉの表面に残留するＳｉＯ２より還元作用により生
ずるものと考えられる。At this time, Cr 0 3 is caused by Cr reacting with rare residual oxygen during vapor deposition, or by heat treatment (sintering) after vapor deposition.
It is thought that this is caused by the reduction action of SiO2 remaining on the surface of Si.

特にＳｉの表面不純物濃度が大きいほど酸化しやすく蒸
着前のＳｉ表面にＳ ｉ０２が残留しやすい。In particular, the higher the surface impurity concentration of Si, the easier it is to oxidize and the more likely Si02 remains on the Si surface before vapor deposition.

コンタクト電極膜剥離頻寒もＳｉの表面不純物濃度が大
きいほど太きい。The frequency of contact electrode film peeling increases as the Si surface impurity concentration increases.

また、Ｃｒと同様に、Ａｅもエッチング液と反応し易い
。Further, like Cr, Ae also tends to react with the etching solution.

本発明の目的は、上記した欠点を除去し、アフタエッチ
によるコンタクト用電極膜の剥離を皆無にし、且つ熱的
、電気的特性にも優れた半導体装置の製法を提供するこ
とにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that eliminates the above-mentioned drawbacks, eliminates peeling of a contact electrode film due to after-etching, and has excellent thermal and electrical characteristics.

この目的を達成するために本発明の特徴とするところは
、蒸着法にて形成したオーミツクコンタクト用電極膜全
面に半田膜゛を緻密に被覆し、その後アフタエツテを行
うことによりアフタエツチ時のエッチ液とコンタクト電
極膜との反応を防止することにある。In order to achieve this object, the present invention is characterized in that the entire surface of the electrode film for ohmic contacts formed by vapor deposition is densely coated with a solder film, and then after-etching is carried out, whereby an etchant is removed during the after-etching. The purpose is to prevent reactions between the contact electrode film and the contact electrode film.

また、その結果としてオーミツクコンタクト用電極膜と
電極リードとの接着も完全となるようにすることにある
。Moreover, as a result, the adhesion between the ohmic contact electrode film and the electrode lead is also made perfect.

以下、この発明の一実施例であるダイオードの製法を第
２図を参照しつつ説明する。Hereinafter, a method for manufacturing a diode which is an embodiment of the present invention will be explained with reference to FIG.

まず、Ｎ型Ｓｉ基板にＰ型を与える不純物を拡散してＰ
Ｎ接合が形成された半導体基体１４の一対の主表面にオ
ーミツクコンタクト用電極として、Ｓｉとのオーミツク
コンタクトの特に良好なＣｒを第１層目、ロウ材と接着
性の良い金属であるＮｉを２層目、Ａｇを３層目に積層
した多層構造の竃極膜１３，１５を真空蒸着法により主
表面全体に形戒する。First, an impurity that gives P type is diffused into an N-type Si substrate.
As ohmic contact electrodes on the pair of main surfaces of the semiconductor substrate 14 on which N junctions are formed, Cr, which has particularly good ohmic contact with Si, is used as the first layer, and Ni, which is a metal with good adhesion to the brazing material, is used as the first layer. The electrode films 13 and 15 having a multilayer structure in which Ag is laminated as the second layer and Ag as the third layer are formed over the entire main surface by vacuum evaporation.

次に、この蒸着電極膜１３，１５上全面に軟質ロウ材、
例えば融点３００℃程度のｐｂ系半田をデイツプ法等に
より被覆形成させる。Next, a soft brazing material is applied to the entire surface of the vapor-deposited electrode films 13 and 15.
For example, a coating of PB solder having a melting point of about 300° C. is formed by a dip method or the like.

このデイップ法とは融点より約５０℃〜８０℃高く加熱
された半田溶液中に半導体素子を浸漬し、薄く且つ均一
な半田層２ ２’， ２ ６’を形成する方法である。This dipping method is a method in which a semiconductor element is immersed in a solder solution heated to about 50 to 80 degrees Celsius above its melting point to form thin and uniform solder layers 22' and 26'.

この半田層の厚みは、溶融半田の温度、フラツクスの種
類等の調整により所定厚みに対し１０％程度のバラツキ
範囲におさえることが可能である。The thickness of this solder layer can be controlled within a range of about 10% variation with respect to a predetermined thickness by adjusting the temperature of the molten solder, the type of flux, etc.

デイツプ法によれば、ピンホールのない緻密な半田膜が
得られる。According to the dip method, a dense solder film without pinholes can be obtained.

次に公知の機械的、化学的手法により半導体基体および
電極膜を整形して第２図に示すような所定の形状に形成
される。Next, the semiconductor substrate and the electrode film are shaped by known mechanical and chemical methods to form a predetermined shape as shown in FIG.

次に主表面全面に被覆した半田２２’，２６’と同じ材
質の半田１２．１６を介して、半導体基体２４０両主表
面に電極リード１７および放熱板１１をＨ２中で加熱す
ることにより接続する。Next, the electrode leads 17 and the heat sink 11 are connected to both main surfaces of the semiconductor substrate 240 by heating them in H2 via the solder 12.16 made of the same material as the solders 22' and 26' coated on the entire main surface. .

電極りード１７の接着面積は、主表面面積に比較し、小
さい。The bonding area of the electrode lead 17 is small compared to the main surface area.

この時、半田層２２’，２６’と接着用半田１２，１６
は組成がほぼ同一の半田なので、溶融時の親和性が良く
、接着性は非常に良好となり、不完全接着部がなく、熱
疲労が少なくなり、サージ耐量は大幅に向上する。At this time, the solder layers 22', 26' and the adhesive solder 12, 16
Since these are solders with almost the same composition, they have good affinity when melted, have very good adhesion, have no incompletely bonded parts, reduce thermal fatigue, and greatly improve surge resistance.

次にこれらの工程を経た半導体素子は，工程中の・・ン
ドリンクその他で生ずるＰＮ接合端部の部分的破損や欠
陥を取り除く為に、アフタエツチを実施スる。Next, the semiconductor device that has gone through these steps is subjected to after-etching in order to remove partial damage or defects at the PN junction end that occur due to linkage or other problems during the process.

このエッチングは、接着の終った金属部品（Ｃｕ製電極
リード１７および放熱板１１）ヘ悪影響を与えてはなら
ないので、影響の少ないアルカリ溶液，主にＮａＯＨ，
ＫＯ Ｈ等の溶液が用いられる。This etching must not have a negative effect on the metal parts (Cu electrode lead 17 and heat sink 11) that have been bonded, so we use an alkaline solution, mainly NaOH, which has little effect.
A solution such as KOH is used.

これらのエッチング液は、上述したように、オーミツク
コンタクト電極に対して活性である。These etchants are active with respect to ohmic contact electrodes, as described above.

本実施例では５乃至１５多程度のＮａＯＨ：水溶液で２
分乃至５分間煮沸エッチングを実施した。In this example, 5 to 15 degrees of NaOH: 2
Boiling etching was performed for 5 minutes to 5 minutes.

本実施例では半田層２ ２’ ， ２ ６’を例えば１
０μ扉の厚さにすることによりエッチング液の浸透は皆
無であった。In this embodiment, the solder layers 2 2' and 2 6' are, for example, 1
By setting the door thickness to 0μ, there was no penetration of the etching solution.

その後アフタエッチの終った半導体基体のＰＮ接合露出
面を密着性の良好なＳｉゴムで被覆してダイオードが完
成する。Thereafter, the exposed PN junction surface of the semiconductor substrate, which has been subjected to after-etching, is covered with Si rubber having good adhesion to complete the diode.

本実施例によれば，従来全体量の４０乃至７５係ものコ
ンタクト電極剥離が発生していたものが皆無となった。According to this embodiment, contact electrode peeling, which conventionally had a total amount of 40 to 75 times, has completely disappeared.

特に低損失を目的にしているダイオードに於いてはコン
タクト抵抗を下げねばならぬ為ダイオード表面濃度を極
力上げているので、本発明の効果は一層顕著であった。Particularly in diodes intended for low loss, the contact resistance must be lowered, so the surface concentration of the diode is increased as much as possible, so the effects of the present invention are even more remarkable.

又、半田の接着性向上により不完全接着部が従来は面積
比で、主表面全面の１５乃至３０係あつたのが、５ｑｌ
）以下となり、電流拡がりも良く、熱疲労耐量で従来の
約２．３倍の向上が得られた。In addition, due to improved solder adhesion, the area ratio of incompletely bonded parts was 15 to 30 on the entire main surface, but now it is 5ql.
) or less, the current spread was good, and the thermal fatigue resistance was improved by about 2.3 times compared to the conventional one.

また、サーシ耐量に於いても従来の５０％向上が確認さ
れている。Furthermore, it has been confirmed that the sash resistance is improved by 50% compared to the conventional method.

以上述べたように、本発明は半導体素子のアフタエッチ
ング液と、半導体基体の電極との反応を防止し、熱約電
気的に優れた半導体装置を高歩留で得るのに効果がある
。As described above, the present invention is effective in preventing the reaction between the after-etching liquid of the semiconductor element and the electrode of the semiconductor substrate, and obtaining a semiconductor device with excellent thermal and electrical properties at a high yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のダイオードの一例を示す断面図、第２図
は本発明の一実施例製法により作製されたダイオードを
示す断面図である。 １１・・・放熱板、１２，１６・・・ロウ材、１３，１
５・・・電極膜、１４・・・半導体基体、１７・・・電
極リード、２２’，２６’・・・半田層。FIG. 1 is a sectional view showing an example of a conventional diode, and FIG. 2 is a sectional view showing a diode manufactured by an embodiment of the manufacturing method of the present invention. 11... Heat sink, 12, 16... Brazing material, 13, 1
5... Electrode film, 14... Semiconductor substrate, 17... Electrode lead, 22', 26'... Solder layer.

Claims (1)

【特許請求の範囲】[Claims] １ 一対の主表面と、少なくとも１つのＰＮ接合とを有
する半導体基体の一対の主表面上の全面にそれそれ一対
のオーミツクコンタクト用電極膜を蒸着法により形成す
る工程と、上記一対のオーミッタコンタクト用電極膜の
少なくとも一方の全面に半田膜を緻密に形成する工程と
他方のオーミツクコンタクト用電極膜に支持電極を接着
し、上記半田膜の一部分のみに上記半田膜の主表面の一
部を残して電極リードを接着する工程と、上記半導体基
体を上記オーミツクコンタクト用電極膜に対して活性を
有するアルカリ性水溶液のエツテング液にてエツテング
する工程とを具備することを特徴とする半導体装置の製
法。1. A step of forming a pair of ohmic contact electrode films by vapor deposition on the entire surface of a pair of main surfaces of a semiconductor substrate having a pair of main surfaces and at least one PN junction, and A step of densely forming a solder film on the entire surface of at least one of the electrode films for contact, and adhering a support electrode to the other electrode film for ohmic contact, and forming a part of the main surface of the solder film only on a part of the solder film. A semiconductor device comprising: a step of bonding an electrode lead while leaving a . Manufacturing method.
JP52137948A 1977-11-18 1977-11-18 Manufacturing method for semiconductor devices Expired JPS5849023B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52137948A JPS5849023B2 (en) 1977-11-18 1977-11-18 Manufacturing method for semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52137948A JPS5849023B2 (en) 1977-11-18 1977-11-18 Manufacturing method for semiconductor devices

Publications (2)

Publication Number Publication Date
JPS5471562A JPS5471562A (en) 1979-06-08
JPS5849023B2 true JPS5849023B2 (en) 1983-11-01

Family

ID=15210442

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52137948A Expired JPS5849023B2 (en) 1977-11-18 1977-11-18 Manufacturing method for semiconductor devices

Country Status (1)

Country Link
JP (1) JPS5849023B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019043950A1 (en) 2017-09-04 2019-03-07 三菱電機株式会社 Semiconductor module and power conversion device

Also Published As

Publication number Publication date
JPS5471562A (en) 1979-06-08

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