JP2579629B2 - Semiconductor electrode formation method - Google Patents

Semiconductor electrode formation method

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Publication number
JP2579629B2
JP2579629B2 JP62058364A JP5836487A JP2579629B2 JP 2579629 B2 JP2579629 B2 JP 2579629B2 JP 62058364 A JP62058364 A JP 62058364A JP 5836487 A JP5836487 A JP 5836487A JP 2579629 B2 JP2579629 B2 JP 2579629B2
Authority
JP
Japan
Prior art keywords
layer
plating layer
semiconductor substrate
solder
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62058364A
Other languages
Japanese (ja)
Other versions
JPS63224325A (en
Inventor
信一 松本
救 森宮
敏孝 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Components Co Ltd
Original Assignee
Toshiba Components Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Components Co Ltd filed Critical Toshiba Components Co Ltd
Priority to JP62058364A priority Critical patent/JP2579629B2/en
Publication of JPS63224325A publication Critical patent/JPS63224325A/en
Application granted granted Critical
Publication of JP2579629B2 publication Critical patent/JP2579629B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体電極形成方法に関する。Description: TECHNICAL FIELD The present invention relates to a method for forming a semiconductor electrode.

〔従来の技術〕[Conventional technology]

従来の半導体電極形成方法は、第4図に示す如く、行
われている。すなわち、先ず、同図(A)に示す如く、
表面を粗面化した例えばシリコンからなる半導体基板1
を用意する。次いで、同図(B)に示す如く、半導体基
板1の表裏両面に蒸着或はメッキによりNi膜2を形成す
る。次いで、これに水素雰囲気中で熱処理を施し、同図
(C)に示す如く、Ni膜2の直下にNi及びSiの酸化物層
3及びSi−Niシリサイド層4を順次形成する。次いで、
同図(D)に示す如く、硝酸と塩酸の混酸により両面の
Ni膜2及び酸化物層3を除去する。然る後、同図(E)
に示す如く、両面のSi−Niシリサイド層4上に再度の蒸
着或はメッキによりNiからなる電極5を形成する。
The conventional method of forming a semiconductor electrode is performed as shown in FIG. That is, first, as shown in FIG.
Semiconductor substrate 1 made of, for example, silicon whose surface is roughened
Prepare Next, as shown in FIG. 1B, a Ni film 2 is formed on both front and back surfaces of the semiconductor substrate 1 by vapor deposition or plating. Next, this is subjected to a heat treatment in a hydrogen atmosphere to form a Ni and Si oxide layer 3 and a Si—Ni silicide layer 4 immediately below the Ni film 2 as shown in FIG. Then
As shown in FIG. 3 (D), the mixed acid of nitric acid and hydrochloric acid
The Ni film 2 and the oxide layer 3 are removed. After that, the same figure (E)
As shown in FIG. 5, an electrode 5 made of Ni is formed on the Si-Ni silicide layers 4 on both surfaces by vapor deposition or plating again.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

しかしながら、上述の従来の半導体電極形成方法で
は、電極形成に際して電極の接着作用を発揮するSi−Ni
シリサイド層4を形成し易くするため、及び、接着面積
を増大させるために半導体基板1の両面に、機械的或は
化学的な表面粗面化を施す。このため、半導体素子の耐
圧特性の劣化及びダメージに起因する割れによる歩留り
低下の問題があった。また、Si−Niシリサイド層4を形
成するためその界面で局部的な空洞が発生し機械的強度
の低下を招く。更に、Si−Niシリサイド層4上のN膜2
及び酸化物層3を混酸で完全に除去することが困難であ
るため、一部の酸化物層3を介在した状態で電極5が形
成される。その結果、電極5の接着強度が弱く電極5剥
離を起こし、素子の信頼性低下を招く問題があった。
However, in the above-mentioned conventional method for forming a semiconductor electrode, the Si-Ni
To facilitate the formation of the silicide layer 4 and to increase the bonding area, both surfaces of the semiconductor substrate 1 are subjected to mechanical or chemical surface roughening. For this reason, there has been a problem that the yield strength is reduced due to cracking caused by deterioration of the breakdown voltage characteristics and damage of the semiconductor element. Further, since the Si-Ni silicide layer 4 is formed, a local cavity is generated at the interface, which causes a decrease in mechanical strength. Further, the N film 2 on the Si-Ni silicide layer 4
Since it is difficult to completely remove the oxide layer 3 with a mixed acid, the electrode 5 is formed with some of the oxide layers 3 interposed. As a result, the bonding strength of the electrode 5 was weak, and the electrode 5 was peeled off.

本発明は、かかる点に鑑みてなされたものであり、素
子の耐圧劣化を防止すると共に割れの発生を防止して歩
留りを向上させ、しかも、電極の接着強度を高めて信頼
性を向上された半導体装置を容易に得ることができる半
導体電極形成方法を提供するものである。
The present invention has been made in view of the above points, and has been developed to prevent the deterioration of the withstand voltage of the element, prevent the occurrence of cracks, improve the yield, and improve the adhesive strength of the electrodes to improve the reliability. An object of the present invention is to provide a method for forming a semiconductor electrode, which can easily obtain a semiconductor device.

〔問題点を解決するための手段〕[Means for solving the problem]

本発明は、表面を粗面化していない半導体基板を、炭
酸ニッケルを主成分とする弗酸浴中に浸漬して電気メッ
キにより前記表面にNiメッキ層を形成する工程と、該半
導体基板を所定温度の半田液中に浸漬して前記Niメッキ
層上に半田層を形成すると共に、前記Niメッキ層の直下
にNiシリサイド層を形成する工程とを具備することを特
徴とする半導体電極形成方法である。
The present invention provides a step of immersing a semiconductor substrate whose surface is not roughened in a hydrofluoric acid bath containing nickel carbonate as a main component to form a Ni plating layer on the surface by electroplating, Forming a solder layer on the Ni plating layer by immersing in a solder solution at a temperature, and forming a Ni silicide layer immediately below the Ni plating layer. is there.

〔作用〕[Action]

本発明に係る半導体電極形成方法によれば、半導体基
板に粗面化を行うことなく電極形成する。このため素子
の耐圧劣化を防止すると共に、割れの発生を防止して歩
留りを向上させることができる。電極形成は、メッキ液
中の電解処理と半田液中での加熱処理にて行う。このた
め、空洞及び酸化物層の発生を防止して高い接着強度で
電極を形成し、素子の信頼性を高めた半導体装置を容易
に提供することができる。
According to the method of forming a semiconductor electrode according to the present invention, an electrode is formed without roughening a semiconductor substrate. For this reason, it is possible to prevent the deterioration of the breakdown voltage of the element and to prevent the occurrence of cracks, thereby improving the yield. The electrodes are formed by electrolytic treatment in a plating solution and heat treatment in a solder solution. For this reason, it is possible to easily provide a semiconductor device in which the electrodes are formed with high adhesive strength by preventing the generation of a cavity and an oxide layer and the reliability of the element is improved.

〔実施例〕〔Example〕

以下、本発明の実施例について図面を参照して説明す
る。先ず、第1図に示す如く、炭酸ニッケル100g,クエ
ン酸30g,弗酸75cc,ラウリル酸ナトリウム40mg,純水1000
ccからなるメッキ液11中に、表面に粗面化処理を施して
いない例えばシリコンからなる半導体基板12を浸漬す
る。次いで、半導体基板12に対向するようにしてNi板か
らなる金属板13を浸漬する。次に、半導体基板12に負の
バイアスが印加し、金属板13に正のバイアスが印加する
ように両者間に電源部14を介在させる。次いで、電源部
14により半導体基板12と金属板13間に所定時間、所定の
電流を通電する。ここで、かかる通電により半導体基板
12の表面に形成するNiメッキ層15の厚さは、その後の熱
処理時にNiシリサイド層とNiメッキ層15間に空洞を発生
させないためには、薄い方が望ましい。しかし、Niメッ
キ層15形成後の半田電極形成の際に、あまりに薄肉であ
ると半田のなじみが極めて悪くなる。よって、必要最小
限の肉厚をNiメッキ層15に付与することが必要である。
かかる観点から半導体基板12の直径が76mmで表面濃度が
1019cm-3の場合、通電電流は0.5Aとし、通電時間は150
秒とするのが望ましい。この場合、厚さ0.05〜0.10μm
のNiメッキ層15を半導体基板12上に形成することができ
る。
Hereinafter, embodiments of the present invention will be described with reference to the drawings. First, as shown in FIG. 1, nickel carbonate 100 g, citric acid 30 g, hydrofluoric acid 75 cc, sodium laurate 40 mg, pure water 1000
A semiconductor substrate 12 made of, for example, silicon whose surface is not subjected to a surface roughening treatment is immersed in a plating solution 11 made of cc. Next, a metal plate 13 made of a Ni plate is immersed so as to face the semiconductor substrate 12. Next, the power supply unit 14 is interposed between the semiconductor substrate 12 so that a negative bias is applied thereto and the metal plate 13 is applied with a positive bias. Next, the power supply
A predetermined current is applied between the semiconductor substrate 12 and the metal plate 13 for a predetermined time. Here, the semiconductor substrate is
The thickness of the Ni plating layer 15 formed on the surface of the substrate 12 is desirably thin so that no void is generated between the Ni silicide layer and the Ni plating layer 15 during the subsequent heat treatment. However, when the solder electrode is formed after the Ni plating layer 15 is formed, if the thickness is too thin, the adaptation of the solder becomes extremely poor. Therefore, it is necessary to provide the Ni plating layer 15 with a necessary minimum thickness.
From this point of view, the diameter of the semiconductor substrate 12 is 76 mm and the surface concentration is
In the case of 10 19 cm -3 , the conduction current is 0.5 A and the conduction time is 150
Desirably seconds. In this case, the thickness is 0.05 ~ 0.10μm
Ni plating layer 15 can be formed on semiconductor substrate 12.

次に、上述のようにしてNiメッキ層15を形成した半導
体基板12を第2図に示す如く、365〜370℃の半田液16中
に約9秒間浸漬する。
Next, as shown in FIG. 2, the semiconductor substrate 12 on which the Ni plating layer 15 is formed is immersed in the solder liquid 16 at 365 to 370 ° C. for about 9 seconds.

然る後、半導体基板12を半田液16から引き出すと、第
3図に示す如く、Niメッキ層15上には半田層17が形成さ
れ、かつ、Niメッキ層15の直下にはNiシリサイド層18が
形成されている。
Thereafter, when the semiconductor substrate 12 is pulled out of the solder liquid 16, a solder layer 17 is formed on the Ni plating layer 15, and a Ni silicide layer 18 is formed immediately below the Ni plating layer 15, as shown in FIG. Are formed.

このようにして、Niシリサイド層18とNiメッキ層15間
に全く空洞を発生させることなく、しかも、半田層17及
びNiメッキ層15の両電極を同時に短時間に形成すること
ができる。また、半導体基板12には粗面化処理を施さな
いので、工程の短縮は勿論のこと、素子の耐圧劣化を防
止すると共に、割れの発生を防止して歩留りを向上させ
ることができる。更に、Si,Ni等の酸化物層ができない
ため半田層17及びNiメッキ層15の各電極を高い接着強度
で形成して信頼性を向上させることができる。
In this way, it is possible to form both electrodes of the solder layer 17 and the Ni plating layer 15 simultaneously in a short time without generating any void between the Ni silicide layer 18 and the Ni plating layer 15. In addition, since the semiconductor substrate 12 is not subjected to a surface roughening treatment, it is possible to not only reduce the number of steps but also prevent the withstand voltage of the element from deteriorating and prevent the occurrence of cracks to improve the yield. Furthermore, since an oxide layer of Si, Ni, or the like cannot be formed, the electrodes of the solder layer 17 and the Ni plating layer 15 can be formed with high adhesive strength to improve reliability.

〔発明の効果〕〔The invention's effect〕

以上説明した如く、本発明に係る半導体電極形成方法
によれば、素子の耐圧劣化を防止すると共に割れの発生
を防止して歩留りを向上させ、しかも、電極の接着強度
を高めて信頼性を向上させた半導体装置を容易に得るこ
とができるものである。
As described above, according to the method of forming a semiconductor electrode according to the present invention, the yield is improved by preventing the breakdown voltage of the element and the occurrence of cracks, and the reliability is improved by increasing the adhesive strength of the electrode. The obtained semiconductor device can be easily obtained.

【図面の簡単な説明】[Brief description of the drawings]

第1図乃至第3図は、本発明の実施例を工程順に示す説
明図、第4図は、従来の半導体電極形成方法を工程順に
示す説明図である。 11……メッキ液、12……半導体基板、13……金属板、14
……電源部、15……Niメッキ層、16……半田液、17……
半田層、18……Niシリサイド層。
1 to 3 are explanatory views showing an embodiment of the present invention in the order of steps, and FIG. 4 is an explanatory view showing a conventional method for forming a semiconductor electrode in the order of steps. 11 ... Plating solution, 12 ... Semiconductor substrate, 13 ... Metal plate, 14
…… Power supply unit, 15… Ni plating layer, 16… Solder liquid, 17 ……
Solder layer, 18 ... Ni silicide layer.

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭50−14275(JP,A) 特開 昭62−209824(JP,A) 特開 昭56−130911(JP,A) 特開 昭52−11766(JP,A) ──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-50-14275 (JP, A) JP-A-62-209824 (JP, A) JP-A-56-130911 (JP, A) JP-A 52-209 11766 (JP, A)

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】表面を粗面化していない半導体基板を、炭
酸ニッケルを主成分とする弗酸浴中に浸漬して電気メッ
キにより前記表面にNiメッキ層を形成する工程と、該半
導体基板を所定温度の半田液中に浸漬して前記Niメッキ
層上に半田層を形成すると共に、前記Niメッキ層の直下
にNiシリサイド層を形成する工程とを具備することを特
徴とする半導体電極形成方法。
A step of immersing a semiconductor substrate whose surface is not roughened in a hydrofluoric acid bath containing nickel carbonate as a main component to form a Ni plating layer on the surface by electroplating; Forming a solder layer on the Ni plating layer by dipping in a solder solution at a predetermined temperature, and forming a Ni silicide layer immediately below the Ni plating layer. .
JP62058364A 1987-03-13 1987-03-13 Semiconductor electrode formation method Expired - Lifetime JP2579629B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62058364A JP2579629B2 (en) 1987-03-13 1987-03-13 Semiconductor electrode formation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62058364A JP2579629B2 (en) 1987-03-13 1987-03-13 Semiconductor electrode formation method

Publications (2)

Publication Number Publication Date
JPS63224325A JPS63224325A (en) 1988-09-19
JP2579629B2 true JP2579629B2 (en) 1997-02-05

Family

ID=13082260

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62058364A Expired - Lifetime JP2579629B2 (en) 1987-03-13 1987-03-13 Semiconductor electrode formation method

Country Status (1)

Country Link
JP (1) JP2579629B2 (en)

Also Published As

Publication number Publication date
JPS63224325A (en) 1988-09-19

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