JPH0620984A - Formation of rear plane electrode for semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method for forming semiconductor device rear plane electrode which allows improved adhesion strength and ohmic characteristics. CONSTITUTION:A part of a semiconductor substrate, for example, a part of the rear surface 12 of a silicon wafer 1, is etched and the etched part is allowed to be the recessed part on the rear surface 12. Therefore, the same recessed part is generated on an electrode 3a formed on the rear surface 12 and when the electrode 3a is adhered on the electrode of a package by solder, the adhesion is strengthened by the mechanical anchor effects. When a phosphorus diffused layer is formed on the rear surface 12 of the silicon wafer 1 as an impurity layer after etching, the ohmic characteristics of the electrode are improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a back surface electrode of a semiconductor device, and more particularly to a method for forming a back surface electrode of a semiconductor device having improved adhesion strength and ohmic characteristics of the back surface electrode.

[0002]

2. Description of the Related Art Conventionally, the following method has been disclosed as a method of forming a back surface electrode of a semiconductor device. That is, in Japanese Unexamined Patent Publication No. 59-220937, the back surface of a semiconductor wafer is plasma-etched to be roughened, and a back surface electrode is formed by vapor deposition on the roughened surface to improve the manufacturing yield and the wafer. The adhesive strength with the back electrode was improved. Further, Japanese Patent Application Laid-Open No. 52-135668 discloses a method in which a back surface of a semiconductor substrate is removed by a gas plasma etching method to a desired thickness and then a metal film is attached to the back surface. Further, when the thickness of the semiconductor wafer is set to a desired value, there is a method of polishing by mechanical polishing or the like and then forming the back electrode as described above. This method is shown in FIGS. In FIG. 21, an impurity diffusion layer 91a is formed on the back surface of the N-type silicon wafer 91. When the thickness of this silicon wafer 91 is too thick, it is polished from the back surface side to a desired thickness T. The polishing surface at this time is the YY surface. As a result, as shown in FIG. 22, the impurity diffusion layer 91 is formed.
a disappears. Thereafter, as shown in FIG. 23, a back surface electrode 92 is formed on the polished surface 91b.

[0003]

When the back surface of the semiconductor wafer is roughened by plasma etching as described above, the protective film on the front surface of the semiconductor wafer is also scraped, so that the front surface of the semiconductor wafer is damaged and the semiconductor device of the semiconductor device is damaged. The characteristics may deteriorate. In plasma etching, the height of the rough surface was several nm at the maximum, and therefore the adhesive strength of the back electrode was not sufficient. In order to obtain ohmic characteristics between the semiconductor wafer and the back surface electrode, it is most effective to introduce impurities into the semiconductor wafer. For example, in the case of an N-type silicon wafer, ohmic characteristics can be easily obtained by introducing phosphorus (P), arsenic (As) or the like into the back surface of the N-type silicon wafer and setting the impurity concentration to 10 ¹⁸ pieces / cm ³ or more. . However, when the desired wafer thickness is obtained, the impurity diffusion layer 91a of FIG.
There is a drawback that ohmic characteristics cannot be obtained. Also,
The method in which impurities are introduced by diffusion or ion implantation after the desired wafer thickness is obtained is not a good measure because it is likely to contaminate the subsequent manufacturing process with polishing powder or the like because polishing is performed during the manufacturing of the semiconductor device. Therefore, an object of the present invention is to eliminate the above-mentioned drawbacks, to prevent the surface of a semiconductor wafer from being damaged, to prevent the characteristics of the semiconductor device from being deteriorated, and to form the back surface electrode of the semiconductor device in which the adhesion strength of the back surface electrode is sufficient. Is to provide a method.

[0004]

In order to solve the above problems, in the first invention of the present application, an etching resistant film having an opening for exposing a part of the substrate is formed on the back surface of the semiconductor substrate. A first step, a second step of etching the back surface of the semiconductor substrate using the etching resistant film as an etching mask, a third step of removing the etching resistant film, and an electrode on the back surface of the substrate. A backside electrode forming method of a semiconductor device including a fourth step of forming. In the second invention, the first step of forming an etching resistant film having an opening exposing a part of the substrate on the back surface of the semiconductor substrate, and the semiconductor substrate using the etching resistant film as an etching mask. A second step of etching the back surface of the semiconductor substrate, a third step of removing the etching resistant film, a fourth step of diffusing impurities on the back surface of the semiconductor substrate, and an electrode formed on the back surface of the substrate. A method of forming a back surface electrode of a semiconductor device including a fifth step is created.

[0005]

In the method of forming the back surface electrode of the semiconductor device having the above structure, a part of the back surface of the semiconductor substrate is etched, so that the etched portion becomes a recessed portion of the back surface. Therefore, a recess similar to this recess is also formed in the electrode formed on the back surface, so that when this electrode is bonded to the electrode of the package by soldering or the like, the bonding can be strengthened by the mechanical anchor effect. Furthermore, impurities can be introduced into the inside of the substrate by diffusing the impurities into the back surface of the semiconductor substrate after the above-described etching, and then the back surface of the substrate is polished in a polishing step to make the substrate have a desired thickness. The impurities introduced into can be left on the substrate. Therefore, when the above-mentioned electrode is formed thereafter, the ohmic characteristics of the electrode can be improved in addition to the mechanical anchor effect described above.

[0006]

Embodiments of the present invention will now be described with reference to the drawings. 1 is a rear view of the first embodiment of the present invention, FIG.
2 is a sectional view taken along the line AA of FIG. 1, FIG. 3 is a sectional view showing the continuation of FIG. 2, and FIG. 4 is a sectional view showing the continuation of FIG. 1 to 4
In, a silicon oxide film 2a as an etching resistant film having an opening 21a exposing a part of the silicon wafer 1 is formed on the back surface 12 of the silicon wafer 1 which is a kind of semiconductor substrate. Back surface 1 of the silicon wafer 1 using 2a as an etching mask
2 is etched, then the silicon oxide film 2a is removed, and an electrode 3a is formed on the back surface 12 of the silicon wafer 1. That is, in FIGS. 1 and 2, before forming a circuit element such as a transistor on the front surface 11 of the N-type silicon wafer 1, a silicon oxide film 2a of 1 μm is formed on the (100) back surface 12 of the N-type silicon wafer 1.
Then, the silicon oxide film 2a is etched to have a plurality of square openings 21a each having a side of 10 to 100 .mu.m. Note that the opening 21a is not formed in the peripheral portion of the back surface 12 so as not to hinder the work of fixing the silicon wafer 1 by drawing a vacuum. The surface 11 of the silicon wafer 1 is covered with a protective film (not shown) such as an oxide film or a nitride film. Next, as shown in FIG. 3, the back surface 12 of the silicon wafer 1 is anisotropically etched through the opening 21a with an organic alkali etching solution (tetramethylammonium hydroxide 20%). By doing so, the etching surfaces are the (100) surfaces 12a and (11).
1) It becomes the surface 12b. Here, the (111) plane 12b is the etching plane because the (111) plane 12b has a high atomic nucleus density. In the anisotropic etching, since the etching rate in the lateral direction is relatively smaller than the etching rate in the depth direction of the silicon wafer 1, the etching that is deeper than the plasma etching is faithful to the pattern of the silicon oxide film 2a. Can be processed. The etching depth at this time is shorter than the length of one side of the opening 21a as shown in FIG. Further, according to the anisotropic etching, the front surface 11 of the silicon wafer 1 is not damaged and the back surface 12 of the silicon wafer 1 can be formed with uniform and reproducible unevenness. Further, as shown in FIG. 4, the silicon oxide film 2a is removed,
On the back surface 12 of the silicon wafer 1, the back surface electrode titanium (T
i), nickel (Ni), and gold (Au) layers 3a are deposited.

FIG. 5 is a rear view of the second embodiment of the present invention, and FIG. 6 is a sectional view taken along line BB of FIG. 5 and 6,
Unlike the case of the first embodiment, there is shown a case where the silicon oxide film 2a has one opening 21a. In this case, one side of the opening 21a is about 2 mm. Others
This is the same as the first embodiment. That is, the back surface electrode 3b is formed on the back surface 42 of the silicon wafer 4. Incidentally, 41 is the front surface of the silicon wafer 4, 42a is the (100) surface of the back surface 42, and 42b is (11) of the back surface 42.
1) surface.

FIG. 7 is a rear view of the third embodiment of the present invention, FIG. 8 is a sectional view taken along line CC of FIG. 7, FIG. 9 is a sectional view showing a continuation of FIG. 8, and FIG. 10 is a continuation of FIG. FIG. 11 is a sectional view showing FIG.
Is a sectional view showing the continuation of FIG. 12, FIG. 12 is a sectional view showing the continuation of FIG. 11, and FIG. 13 is a sectional view showing the continuation of FIG. Figure 7-
In FIG. 13, a silicon oxide film 2b as an etching resistant film having a plurality of openings 21b exposing a part of the silicon wafer 5 is formed on the back surface 52 of the silicon wafer 5 which is a kind of semiconductor substrate. The back surface 52 of the silicon wafer 5 is etched by using the silicon oxide film 2b as an etching mask, then the silicon oxide film 2b is removed, and then the silicon wafer 5 is removed.
A phosphorus diffusion layer 53 as an impurity diffusion layer is formed on the back surface 52 of the silicon wafer 5, and in the back surface polishing step, the silicon wafer 5
After being polished to a desired thickness, the electrode 3c is formed on the back surface 52 of the silicon wafer 5. That is, in FIG.
In FIG. 8, a silicon oxide film 2b having a thickness of 1 μm is formed on the (100) back surface 52 of the N-type silicon wafer 5, and then a plurality of square openings 21b each having a side of 10 to 100 μm are etched in the silicon oxide film 2b. To form. The surface 51 of the silicon wafer 5 is covered with a protective film (not shown) such as an oxide film / nitride film.

Next, as shown in FIG. 9, the opening 21
By b, the back surface 52 of the silicon wafer 5 is anisotropically etched with an organic alkali etching solution (tetramethylammonium hydroxide 20%). By doing so, the etching surface becomes the (100) surface 52a and the (111) surface 52b. Here, the (111) plane 52b
Is the etching surface because the (111) surface 52b has a high atomic nucleus density as in the first embodiment.
The etching depth at this time is similar to that in the case of FIG. Further, as shown in FIG. 10, the silicon oxide film 2b is removed, and then a phosphorus diffusion layer 53 is formed on the back surface 52 of the silicon wafer 5 as shown in FIG. Next, as shown in FIG. 12, mechanical polishing is performed on the XX plane to bring the thickness of the silicon wafer 5 to a desired value. In this case, the phosphorus diffusion layer 53 remains at the etched portion even after the mechanical polishing. Next, as shown in FIG. 13, back surface electrodes Ti, Ni, and Au layers 3c are deposited on the back surface 52 of the silicon wafer 5.
Reference numeral 54 is the mechanical polishing surface. In this case, since the phosphorus diffusion layer 53 remains as described above, the back surface electrode 3c having excellent ohmic characteristics can be formed. Further, since it is not necessary to form the impurity diffusion layer after polishing, there is no contamination in the manufacturing process of the semiconductor device.

FIG. 14 is a rear view of the fourth embodiment of the present invention,
FIG. 15 is a sectional view taken along the line DD of FIG. 14 and 15
In FIG. 6, unlike the case of the third embodiment, the case where the number of the openings 21b of the silicon oxide film 2b is one is shown. Others are the same as those in the third embodiment. That is, the back surface electrode 3d is formed on the back surface 62 of the silicon wafer 6. Reference numeral 61 is the front surface of the silicon wafer 6, 62a is the (100) surface of the back surface 62, 62b is the (111) surface of the back surface 62, 63 is a phosphorus diffusion layer, and 64 is a mechanical polishing surface.

FIG. 16 is a rear view of the first application example of each of the above embodiments, and FIG. 17 is a sectional view taken along line EE of FIG. Figure 16
In FIG. 17, the surface 71 of the back surface electrode of the vertical power MOSFET 7a is bonded to the electrode 72 of the package by the solder layer 73. In this case, the front surface 7 of the back electrode
Since one concave portion 71a is formed in one, a mechanical anchoring effect is produced, so that reliability of adhesion is improved. For this reason, the front surface 71 of the back electrode and the solder layer 7 are subject to heat generation due to power loss of the semiconductor device and changes in ambient temperature.
Even if 3 expands or contracts, the adhesion between the two is strong and the peeling does not occur easily. The solder layer 73 may be replaced with a conductive paste. Further, since the contact area of the front surface 71 of the back electrode is increased by the recess 71a, ohmic characteristics are improved.

FIG. 18 is a rear view of the second application example of each of the above-mentioned embodiments, and FIG. 19 is a sectional view taken along the line FF of FIG. Figure 18
In FIG. 19, the surface 76 of the back electrode of the vertical power M0SFET 7b is adhered to the electrode 77 of the package by the solder layer 78. In this case, since the four recesses 76a are formed on the surface 76 of the back electrode,
Since the mechanical anchoring effect is generated as in the case of the first application example, the reliability of adhesion is improved and the ohmic characteristics are improved. The solder layer 78 may be replaced with a conductive paste. In this case, as described above, 4
Since the individual recesses 76a are formed, the bonding strength and ohmic characteristics are improved as compared with the first application example.

FIG. 20 is a vertical sectional view of the fifth embodiment of the present invention, which corresponds to FIG. In FIG. 20, on the (110) back surface 82 of the silicon wafer 8, K
A plurality of deep grooves 8 are formed by etching using an OH aqueous solution.
2a is formed. When the (110) plane is etched with a KOH aqueous solution, very good anisotropic etching is performed, and a deep groove is formed. The deep groove 82a has a mechanical anchoring effect similar to or higher than the recesses 71a and 76a of the front surfaces 71 and 76 of the back electrode. Reference numeral 81 is the surface of the silicon wafer 8. The method of forming the back surface electrode of the semiconductor device according to the fifth embodiment can be applied to a bipolar transistor.

[0014]

As described above in detail, according to the method for forming a semiconductor back surface electrode of the present invention, the adhesion strength when the back surface electrode of the semiconductor device is bonded to the package electrode by soldering or the like, Furthermore, the ohmic characteristics of this electrode can be improved.

[Brief description of drawings]

FIG. 1 is a rear view of a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is a sectional view of the first embodiment, showing the continuation of FIG.

FIG. 4 is a sectional view of the first embodiment, showing a continuation of FIG.

FIG. 5 is a back view of the second embodiment of the present invention.

6 is a sectional view taken along line BB of FIG.

FIG. 7 is a rear view of the third embodiment of the present invention.

FIG. 8 is a sectional view taken along line CC of FIG.

9 is a sectional view of the third embodiment, showing the continuation of FIG. 8;

FIG. 10 is a sectional view of the third embodiment, showing the continuation of FIG. 9;

FIG. 11 is a sectional view of the third embodiment, showing the continuation of FIG. 10;

12 is a cross-sectional view of the third embodiment, showing the continuation of FIG.

FIG. 13 is a sectional view of the third embodiment, showing the continuation of FIG. 12;

FIG. 14 is a back view of the fourth embodiment of the present invention.

15 is a cross-sectional view taken along the line DD of FIG.

FIG. 16 is a back view of a first application example of each of the embodiments.

17 is a sectional view taken along line EE in FIG.

FIG. 18 is a back view of a second application example of each of the embodiments.

19 is a sectional view taken along line FF of FIG.

FIG. 20 is a sectional view of a fifth embodiment of the present invention.

FIG. 21 is a sectional view of a conventional example.

FIG. 22 is a cross-sectional view of a conventional example, showing the continuation of FIG. 21.

FIG. 23 is a cross-sectional view of the conventional example, showing the continuation of FIG. 22.

[Explanation of symbols]

1, 4, 5, 6, 8 Silicon wafer 12, 42, 52, 62, 82 Silicon wafer back surface 2a, 2b Silicon oxide film 21a, 21b Silicon oxide film opening 3a, 3b, 3c, 3d Back surface electrode 53, 63 Phosphorus diffusion layer

Claims (2)

[Claims] 1. A first step of forming an etching resistant film having an opening for exposing a part of the substrate on the back surface of the semiconductor substrate, and the back surface of the semiconductor substrate using the etching resistant film as an etching mask. A second step of etching, and a third step of removing the etching resistant film,
And a fourth step of forming an electrode on the back surface of the substrate. 2. A first step of forming an etching resistant film having an opening exposing a part of the substrate on the back surface of the semiconductor substrate, and the back surface of the semiconductor substrate using the etching resistant film as an etching mask. A second step of etching, and a third step of removing the etching resistant film,
A method of forming a back surface electrode of a semiconductor device, comprising: a fourth step of diffusing impurities on the back surface of the semiconductor substrate; and a fifth step of forming an electrode on the back surface of the substrate.