JPS6310894B2 - - Google Patents
Info
- Publication number
- JPS6310894B2 JPS6310894B2 JP4143581A JP4143581A JPS6310894B2 JP S6310894 B2 JPS6310894 B2 JP S6310894B2 JP 4143581 A JP4143581 A JP 4143581A JP 4143581 A JP4143581 A JP 4143581A JP S6310894 B2 JPS6310894 B2 JP S6310894B2
- Authority
- JP
- Japan
- Prior art keywords
- nickel
- layer
- nickel layer
- sputtering
- semiconductor wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 68
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 34
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052709 silver Inorganic materials 0.000 claims abstract description 13
- 239000004332 silver Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 11
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims abstract description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 5
- 239000011574 phosphorus Substances 0.000 claims abstract description 5
- 238000001035 drying Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 abstract description 30
- 238000004544 sputter deposition Methods 0.000 abstract description 8
- 238000005245 sintering Methods 0.000 abstract description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 229910001873 dinitrogen Inorganic materials 0.000 abstract description 3
- 239000002344 surface layer Substances 0.000 abstract description 2
- 238000005530 etching Methods 0.000 abstract 1
- 238000004299 exfoliation Methods 0.000 abstract 1
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 238000007747 plating Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
- G11B20/1806—Pulse code modulation systems for audio signals
- G11B20/1809—Pulse code modulation systems for audio signals by interleaving
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
Abstract
Description
【発明の詳細な説明】
本発明は半導体ウエハの裏面への裏面電極形成
方法の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a method for forming backside electrodes on the backside of a semiconductor wafer.
例えばトランジスタ、またはダイオードはより
高周波化、高出力化、高速化、または高性能化を
図る目的で半導体ウエハの裏面に低抵抗の金属を
付着させてオーミツクコンタクトを良くするた
め、更に半導体チツプを外装に組立てる際に組立
を容易にするために、裏面電極を形成する方法が
採られている。 For example, transistors or diodes are made by attaching low-resistance metal to the backside of a semiconductor wafer to improve ohmic contact in order to achieve higher frequencies, higher output, higher speed, or higher performance. In order to facilitate assembly when assembling to the exterior, a method is adopted in which a back electrode is formed.
この裏面電極形成方法の従来の方法は次のとお
りである。まず、半導体ウエハの表面にワツクス
を塗布し、裏面の酸化膜をフツ酸で除去した後、
裏面にニツケルを無電解メツキにより付着させ
る。その後、400〜600℃の窒素ガス雰囲気中でシ
ンターを行ない、続いてスパツタリング法で数
100Åの厚さのニツケルをスパツタエツチングし、
連続して銀をスパツタデポジシヨンさせていた。 The conventional method for forming this back electrode is as follows. First, wax is applied to the front surface of the semiconductor wafer, and the oxide film on the back surface is removed with hydrofluoric acid.
Nickel is attached to the back side by electroless plating. After that, sintering is performed in a nitrogen gas atmosphere at 400 to 600℃, followed by several sputtering methods.
Sputter etching 100Å thick nickel,
Silver was deposited continuously.
ところで、このような形成方法においては、ワ
ツクスの塗布・除去作業、メツキ作業、スパツタ
リング作業などと相当な作業時間と薬品類とを費
やしていた。また、前記のワツクスがニツケルメ
ツキ液中に溶け込んだり、また半導体ウエハから
ワツクスを完全に除去することが容易でなく、電
気的特性上、信頼性上からも不具合を生じてい
た。 However, in such a forming method, a considerable amount of work time and chemicals are required for wax application/removal work, plating work, sputtering work, etc. Furthermore, the wax dissolves into the nickel plating solution, and it is not easy to completely remove the wax from the semiconductor wafer, causing problems in terms of electrical characteristics and reliability.
それ故、本発明の目的は、半導体素子の電気的
特性を低下さすことがなく、しかもドライプロセ
スのみで裏面電極を形成することが可能な方法を
提供することである。 SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method that does not deteriorate the electrical characteristics of a semiconductor element and can form a back electrode using only a dry process.
このような目的を達成するために本発明は、リ
ンを含有したニツケルと、銀とを材料にして、蒸
着またはスパツタリングによりニツケル―銀の二
層構造の裏面電極を形成する方法を提供する。 To achieve these objects, the present invention provides a method for forming a back electrode with a two-layer structure of nickel and silver by vapor deposition or sputtering using phosphorous-containing nickel and silver as materials.
以下、実施例を用いて本発明を詳細に説明す
る。 Hereinafter, the present invention will be explained in detail using Examples.
第１図〜第３図は、本発明に係る裏面電極形成
方法の一実施例の主要段階を示す断面図である。 1 to 3 are cross-sectional views showing the main steps of an embodiment of the method for forming a back electrode according to the present invention.
まず、第１図に示すように、表面電極形成まで
完了した半導体ウエハ１の裏面１１をラツピング
して半導体ウエハ１を所望の厚さにする。次に、
第２図に示すように、半導体ウエハ１の裏面１１
をスパツタエツチングして酸化した表面層を除去
し、リンを例えば２〜10重量パーセント含有した
ニツケルを材料にしてニツケル層２を８〜12kÅ
の厚さにスパツタデポジシヨンする。つづいて、
第３図に示すように、ニツケル層２を数100Åの
厚さスパツタエツチング、更に、銀層３を３〜
6kÅの厚さにスパツタデポジシヨンしたのち、
400〜600℃のシンター炉で、窒素ガス雰囲気中で
シンターリングを行い、半導体ウエハ１の裏面１
１とニツケル層２との間のオーミツクコンタク
ト、更にニツケル層２と銀層３との間のオーミツ
クコンタクトを得て裏面電極形成を完了する。 First, as shown in FIG. 1, the back surface 11 of the semiconductor wafer 1, on which the formation of front surface electrodes has been completed, is wrapped to give the semiconductor wafer 1 a desired thickness. next,
As shown in FIG. 2, the back surface 11 of the semiconductor wafer 1
The oxidized surface layer is removed by sputter etching, and the nickel layer 2 is made of nickel containing, for example, 2 to 10 percent by weight of phosphorus to form a nickel layer 2 of 8 to 12 kÅ.
Spats deposit to a thickness of . Continuing,
As shown in FIG. 3, the nickel layer 2 is sputter etched to a thickness of several hundred Å, and the silver layer 3 is
After sputter deposition to a thickness of 6kÅ,
Sintering is performed in a nitrogen gas atmosphere in a sintering furnace at 400 to 600°C, and the back side 1 of the semiconductor wafer 1 is
Ohmic contact between nickel layer 1 and nickel layer 2 and ohmic contact between nickel layer 2 and silver layer 3 is obtained to complete the formation of the back electrode.
このようにリンを含有したニツケルを裏面電極
材料に用いることにより、シンターリング時にニ
ツケル表面の酸化を防止することができ、半導体
ウエハ１の裏面１１とニツケル層２との界面およ
びニツケル層２と銀層３との界面での剥離も生じ
ることはなくなる。 By using phosphorous-containing nickel as the back electrode material, oxidation of the nickel surface during sintering can be prevented, and the interface between the back surface 11 of the semiconductor wafer 1 and the nickel layer 2 and the interface between the nickel layer 2 and the silver Peeling at the interface with layer 3 also no longer occurs.
更に、ドライプロセスのみで作業が可能にな
り、作業能率も向上し、メツキ方法のようにワツ
クスを使用しないため半導体素子の信頼性の向上
も期待できることは多大である。 Furthermore, it is possible to work with only a dry process, improving work efficiency, and since wax is not used unlike the plating method, it is expected that the reliability of semiconductor devices will be greatly improved.
本実施例は、トランジスタ、ダイオードに適用
した場合について述べたものであるが、この発明
が半導体集積回路（IC）にも応用できることは
いうまでもない。 Although this embodiment describes the case where it is applied to a transistor and a diode, it goes without saying that the present invention can also be applied to a semiconductor integrated circuit (IC).
以上説明したように、この発明による裏面電極
形成方法においては、半導体ウエハの裏面にこの
裏面との良好なオーミツクコンタクトを得るため
に、この裏面側から順次、ニツケル層、銀層をド
ライプロセスで形成すると共にニツケル層形成の
材料にリンを含有したニツケルを用いるので、作
業能率が向上し、また、ニツケルが酸化しないの
でニツケル層と半導体ウエハの裏面および銀層と
の間の界面での剥離を防止することができ、かつ
ワツクスを使用しないので半導体素子の信頼性を
向上させることができる。 As explained above, in the back electrode forming method according to the present invention, in order to obtain good ohmic contact with the back surface of the semiconductor wafer, a nickel layer and a silver layer are sequentially formed on the back surface of the semiconductor wafer using a dry process. Since nickel containing phosphorus is used as the material for forming the nickel layer, work efficiency is improved, and since nickel does not oxidize, peeling at the interface between the nickel layer and the back surface of the semiconductor wafer and the silver layer is prevented. This can be prevented, and since wax is not used, the reliability of semiconductor devices can be improved.
第１〜第３図はこの発明による裏面電極形成方
法の一実施例の主要段階を示す断面図である。
図において、１は半導体ウエハ、１１は半導体
ウエハ１の裏面、２はニツケル層、３は銀層であ
る。
1 to 3 are cross-sectional views showing the main steps of an embodiment of the method for forming a back electrode according to the present invention. In the figure, 1 is a semiconductor wafer, 11 is the back surface of the semiconductor wafer 1, 2 is a nickel layer, and 3 is a silver layer.
Claims (1)
ーミツクコンタクトを得るために、この裏面側か
ら順次、ニツケル層、銀層をドライプロセスで形
成すると共にニツケル層形成の材料にリンを含有
したニツケルを用いることを特徴とする裏面電極
形成方法。1 In order to obtain good ohmic contact with the back surface of the semiconductor wafer, a nickel layer and a silver layer are sequentially formed from this back surface side by a dry process, and nickel containing phosphorus is used as the material for forming the nickel layer. A method for forming a back electrode, characterized in that it is used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4143581A JPS57154845A (en) | 1981-03-19 | 1981-03-19 | Forming method for rear face electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4143581A JPS57154845A (en) | 1981-03-19 | 1981-03-19 | Forming method for rear face electrode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57154845A JPS57154845A (en) | 1982-09-24 |
| JPS6310894B2 true JPS6310894B2 (en) | 1988-03-10 |
Family
ID=12608286
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4143581A Granted JPS57154845A (en) | 1981-03-19 | 1981-03-19 | Forming method for rear face electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57154845A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0280435U (en) * | 1988-12-12 | 1990-06-21 |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02163971A (en) * | 1988-12-16 | 1990-06-25 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and its manufacture |
-
1981
- 1981-03-19 JP JP4143581A patent/JPS57154845A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0280435U (en) * | 1988-12-12 | 1990-06-21 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57154845A (en) | 1982-09-24 |
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