JPS5845117B2 - Memory protection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory protection system, and more particularly to a memory protection system when spike noise occurs in a memory activation signal line sent from an external device in a memory device.

If spike noise occurs in the memory activation signal line sent from an external device to the memory device, this spike noise will occur in various timing signals created from the memory activation signal, causing malfunction of the memory device and destruction of stored information. Cause.

A conventional timing creation method is shown in FIG.

In FIG. 1, RDST, WR8T, and RFST are memory activation signals, representing a read activation signal, a write activation signal, and a refresh activation signal, respectively.

Also RDCY. WRCY and RFCY represent memory cycle signals, which are a read cycle signal, a write cycle signal, and a refresh cycle signal, and are held at the II It level during each cycle period.

The memory activation signal is sent to the timing generation circuit 2 through the Nant gate 1, where various timings (TMAo,
TMBo, ---...TMCo) and flip-flop (FF) set clock, flip-flop (F
F) A reset clock is created.

An example of time relationships such as various timings is as shown in FIG.

Furthermore, each memory cycle signal is created from the memory activation signal.

The read start signal RDST is generated by setting a flip-flop FF(1)5 through a NOT gate 4 and a NAND gate 5, and the logical sum of the output of the flip-flop FF(1)5 and the read start signal is generated by a NAND gate 7. , becomes the read cycle signal RDCY.

The write activation signal WR8T sets the flip-flop FF(2) 10 through the NOT gate 8 and the Nant gate 9, and the logical sum of the output of the flip-flop FF(2) 10 and the write activation signal is created by the Nant gate 11 to complete the write cycle. The signal becomes WRCY.

The refresh start signal RFST is applied to the flip-flop FF(3)1 through the not gate 12 and the Nant gate 13.
4 is set, and the logical sum of the output of the flip-flop FF(3) 14 and the write activation signal is created by the Nant gate 15 and becomes the refresh cycle signal RFCY.

In each flip-flop, S is a set terminal, R is a reset terminal, and Q is an inverted output terminal, and each flip-flop is set at the fall of the input signal to the S terminal.

The above timing (TMAo, TMBo, -...T
MCo) is sent to the timing control circuit 3, where it receives memory cycle signals RDCY and WRCY.

After being controlled by the RFCY signal, it is sent to the location where it is needed.

The timing of receiving this control is TMA, TMB,...
..., TMC, now TMA reads, writes,
Common timing for each refresh cycle, T
MB is an unnecessary timing during the refresh cycle,
Assuming that TMC is a timing required only during a write cycle, a conventional timing control circuit has a configuration as shown in FIG.

In such a configuration, the write activation signal WR
Let us consider a case where spike noise occurs in the phase when the 8T signal is turned on.

When spike noise occurs as shown in the time chart in Figure 3, abnormal timing does not occur because TMC is gated by the WRCY signal as shown in Figure 2, but TMA and TMB are gated by the WRCY signal. Abnormal timing occurs because this is not done.

FIG. 4 shows an example where spike noise occurs in the memory activation signal.

For two identical memory devices A and D, an external device (
The memory start signal MST is switched from the memory access control device) by the memory access switching signals MACA and MACB, and the memory start signal M is sent to one of the memory devices.
If you use the method of sending STA or MSTB,
When a situation (at the time of failure) occurs in which MACA and MACB are delayed with respect to MST, spike noise is generated in the memory activation signal line of the non-selected memory device, as shown in the time chart of FIG.

An object of the present invention is to provide a memory protection method that protects a memory device against spike noise that appears in such a phase and controls the device so as not to transmit abnormal timing even when spike noise occurs. The invention is
By inputting any one of multiple types of memory activation signals, various timing signals are created, and the flip-flop set clock and flip-flop reset are delayed from the activation time of the memory activation signal. A flip-flop that is set when the memory start signal is input at the time when the flip-flop set clock is generated and is reset by the flip-flop reset clock is made to correspond to each of the plurality of types of memory start signals. In a memory device that generates an OR signal of the memory write signal and the output signal of its corresponding flip-flop as a memory cycle signal each time the memory start signal is input, the memory cycle signal is created by the plurality of memory start signals. The present invention is characterized in that the various timing signals are all gated with a memory cycle signal corresponding to the memory activation signal and then sent out.

Next, examples of the present invention will be described.

Since only the timing control circuit 30 is different from the conventional system shown in FIG.
It will look like the figure.

FIG. 5 shows an example of a control method for TMA and TMB.

As mentioned earlier, TMA is the timing commonly required during read, write, and refresh cycles, and TMB
is a timing that is unnecessary during the refresh cycle and necessary during the read and write cycles.

Regarding the TMA, the timing TMAo from the timing generation circuit 2 is gated by the read cycle signal RDCY at the Nant gate 20, gated by the write cycle signal WRCY at the Nant gate 21, and gated by the refresh cycle signal RFCY at the Nant gate 22. .

Therefore, TMA is not output as a signal from the AND gate 23 unless any memory cycle signal is present.

Regarding TMB, the timing TMBo from the timing generation circuit 2 is gated by the read cycle signal RDCY at the Nant gate 24, and
is gated by write cycle signal WRCY.

Therefore, unless either the read cycle signal or the write cycle signal is present, the TMB is at the AND gate 2.
6 is not output as a signal.

Note that the timing TMC required only during the write cycle
Since the circuit shown in FIG. 2 may be used, the circuit shown in FIG. 5 is omitted.

If spike noise occurs in the memory activation signal,
As shown in FIG. 3, the timing generation circuit 2 generates timing signals TMAo, TMBo, TMCo, a flip-flop set clock, and a flip-flop reset clock.

At this time, the timing at which the flip-flop setting clock is generated is set so that it occurs after the spike noise has disappeared, and each flip-flop is not operated by the flip-flop setting clock.

Therefore, an erroneous signal is generated in each memory cycle signal only when spike noise occurs.

On the other hand, each timing signal TMAo, TMBo. TMCo
The time point at which this occurs is also set to occur after the spike noise has disappeared.

Therefore, the TM that is erroneously generated due to spike noise
Each memory cycle signal RDCY, WRCY at the time of Ao, TMBo, TMCo.

FRCY does not appear, so the timings TMA, TMB gated to each of these memory cycle signals
, TMC are never output.

In addition to the three types of timing mentioned above, the timing required for reading and refreshing, and the timing required for writing and refreshing can be determined by changing the memory cycle signal and using the TMB.
Malfunctions can be prevented by performing control similar to TMC by changing the memory cycle signal for the timing required only during the read cycle and the timing required only during the refresh cycle.

As described above, according to the present invention, when spike noise occurs in the memory activation signal line in the phase in which the memory activation signal is turned on, the timing control circuit blocks the abnormal timing that occurs due to this, thereby effectively protecting the memory. It has the advantage of being able to

[Brief explanation of the drawing]

Figure 1 shows a conventional timing creation method in a memory device, Figure 2 shows details of the timing control circuit in Figure 1,
FIG. 3 is a time chart showing the operation of FIG. 1, FIG. 4 is an example of spike noise generation, and FIG. 5 is an example of a timing control circuit according to an embodiment of the present invention. In FIG. 5, TMAo and TMBo are timing signals from a timing generation circuit, RDCY is a read cycle signal, WRCY is a write cycle signal, RFCY is a refresh cycle signal, and TMA. TMB is a timing signal to each part in the memory, 20-2
2, 24, and 25 are Nant gates, and 23°26 is an AND gate.

Claims (1)

[Claims] 1. By inputting any one of the memory activation signals of multiple types of memory activation signals, various timing signals are created, and the flip-flop set clock and flip-flop are delayed from the activation time of the memory activation signal. A preset clock is created, and a flip-flop that is set when the memory start signal is input at the time when the flip-flop set clock is generated and is reset by the flip-flop reset clock corresponds to each of the plurality of types of memory start signals. In a memory device that generates a logical OR signal of the memory activation signal and its corresponding flip-flop output signal as a memory cycle signal each time the memory activation signal is input, the memory activation signal is generated by the plurality of memory activation signals. After gating all the various timing signals with the memory cycle signal corresponding to the memory activation signal,
A memory protection method characterized by transmitting data.