JPS5844798A - Method of producing printed circuit board - Google Patents

Method of producing printed circuit board

Info

Publication number
JPS5844798A
JPS5844798A JP14324581A JP14324581A JPS5844798A JP S5844798 A JPS5844798 A JP S5844798A JP 14324581 A JP14324581 A JP 14324581A JP 14324581 A JP14324581 A JP 14324581A JP S5844798 A JPS5844798 A JP S5844798A
Authority
JP
Japan
Prior art keywords
laminate
hole
layer
plating
copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14324581A
Other languages
Japanese (ja)
Inventor
松本 正重
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP14324581A priority Critical patent/JPS5844798A/en
Publication of JPS5844798A publication Critical patent/JPS5844798A/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明はプリント配線板(以下配線板と称す)の製造方
法に関し、特にスルーホールの内壁面に光化学反応で選
択的に触媒金属層を形成させ、さらに無電解めっきによ
って、導体層を形成する配線板の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a printed wiring board (hereinafter referred to as a wiring board), and in particular, to selectively form a catalytic metal layer on the inner wall surface of a through hole by a photochemical reaction, and further by electroless plating. , relates to a method of manufacturing a wiring board on which a conductor layer is formed.

近年IC,L8I等の電子デバイスの高集積化に伴なっ
て、配線板に対しては兼装密鼠を向上させる目的から1
回路パターンの細線化、スルーホールの孔径の゛小孔径
比、高積増化に伴なう板厚増大などの傾向が高t−tて
きている。そのために配線板製造に除しては電気的高値
粗性上からも高精度化を図ることが必要である。一方、
mii性を考直すると製造時の高歩留りを維持すること
も重要でおる。こルらの対策として1回路パターンの細
−化・高精度化に対しては、エツチド・フォイル法とア
ディティブ法の双方から稙々の試みがなさnている。
In recent years, with the increasing integration of electronic devices such as ICs and L8Is, wiring boards have become more compact with the aim of improving packaging density.
Trends such as thinning of circuit patterns, small hole diameter ratio of through holes, and increase in plate thickness due to increase in volume are becoming higher. For this reason, in manufacturing wiring boards, it is necessary to achieve high precision from the viewpoint of high electrical roughness. on the other hand,
When considering mii characteristics, it is also important to maintain a high yield during manufacturing. As a countermeasure to these problems, various attempts have been made to make each circuit pattern thinner and more precise, using both the etched foil method and the additive method.

そのうち前者のエツチド・フォイル法では銅箔の1rM
薄化(以下(J ′l’ e箔と呼ぶ)゛、電気めっき
厚の均一化およびフォト印刷におけるフォ)L5シスト
印刷設備の改善が試みらnている。
In the former etched foil method, the copper foil is 1rM.
Attempts have been made to improve thinning (hereinafter referred to as J'l'e foil), uniformity of electroplating thickness, and photoprinting of L5 system printing equipment.

しかし、電気めっきにおける膜厚の均一化は特に婦しく
、回路パターンの細線化・高精度化を阻害している。一
方、後者の7デイテイプ法においては細線の回路パター
ンのため回路パターンと積層板の接層強にの確保が離し
い。さらに内層に導体層を含んでいる多層基板の場合に
は5回路パターンと積層板との接*1強固にするため通
常、クロム酸と硫酸の混液で積層板派内の粗化エツチン
グをするが、この際に孔内壁に露出した導体ノーが同時
にエツチングさn内層導体の信頼性に忌影響を及はし好
ましくない。
However, the uniformity of film thickness in electroplating is particularly difficult, and this hinders the development of finer lines and higher precision in circuit patterns. On the other hand, in the latter 7-day tape method, it is difficult to ensure strong contact between the circuit pattern and the laminate because the circuit pattern is a thin line. Furthermore, in the case of a multilayer board that includes a conductor layer in the inner layer, in order to strengthen the contact*1 between the 5-circuit pattern and the laminate, the inside of the laminate is usually roughened and etched with a mixture of chromic acid and sulfuric acid. At this time, the conductor exposed on the inner wall of the hole is etched at the same time, which adversely affects the reliability of the inner layer conductor, which is not preferable.

また1回路パターンを形成する無電解鋼めっき層は、物
性的に電解鋼めっき層に比べて抗張力が省る反曲、積層
板は大きな線#張車を有するために、無電解鋼めっきで
形成さnた回路パターンはこnに抗しきnなくな0.熱
的因子の入っ几用途では高い頗匿で回路パターンの断線
が発生し信籾性上好ましくない。基板のスルーホール孔
径が小さく板厚が厚くなった場合、すなわち孔径対板厚
比(アスペクト比)が大きくなった場合、電気′めっき
でスルーホール孔内壁に均一にめっきを被着させること
は極めて国難であり1文献、カッパープレーティングア
ドパンストyルデレイヤーボードじCopper Pl
ating Advanced Multilayer
Hoards’(Il’U*1976  Fall M
eeting))によnばアスペクト比l:6のときめ
、っきの付き回り90饅、アスペクト比1:lOのとき
70%と、高密度配線基板に対してはめっきの付き回り
が不十分である。一方、アティティプ法ではC上記文献
によILばアスペクト比が大きくなってもめっきの付き
回りは十分であり100%となる。しかし前述゛の如く
内層に導体(ロ)路を含んだ多層基板に対しては内層接
続の信頼性に問題を生じて、高密度配線基板に対しては
十分な製造方法とはいえない。このために、内層導体パ
ターンt−Vする銅張り積層、板の表面に予め回路パタ
ーンをエツチングで形成したのち孔を穿設し、孔内壁に
触媒液を塗布し、−孔内壁に選択的に紫外線を照射し、
触媒金属層を形成し、無電解めっきで導体層を形成して
微細線化さ1した高精度パターンを有する配線基板の製
造方法を提案した。しかし、この方法は紮外脳を照射し
た孔壁のみに光還元”反応で触媒金属を析出させるため
、凹凸のめる孔fitまたはアスペクト比の大@な孔壁
に均一に紫外線を照射することは離しいと云う欠点がめ
った。
In addition, the electroless steel plating layer that forms one circuit pattern is curved, which reduces tensile strength compared to the electrolytic steel plating layer, and the laminate has a large wire tension wheel, so it is formed with electroless steel plating. A small circuit pattern has no resistance to this. In applications where thermal factors are present, the high degree of obscurity may cause disconnection of the circuit pattern, which is unfavorable in terms of reliability. When the through-hole diameter of the board is small and the board thickness is thick, that is, when the hole diameter to board thickness ratio (aspect ratio) becomes large, it is extremely difficult to apply plating uniformly to the inner wall of the through-hole using electroplating. It is a national disaster and 1 document, Copper Plating Adpanst Y Rudelayer Board Copper Pl
Ating Advanced Multilayer
Hoards'(Il'U*1976 Fall M
When the aspect ratio is l:6, the plating coverage is 90%, and when the aspect ratio is 1:lO, the plating coverage is 70%, which is insufficient for high-density wiring boards. It is. On the other hand, in the Atitip method, the coverage of the plating is sufficient and becomes 100% even if the aspect ratio becomes large, according to the above-mentioned literature. However, as mentioned above, for multilayer boards containing conductor paths in the inner layers, a problem arises in the reliability of the inner layer connections, and this method cannot be said to be sufficient for manufacturing high-density wiring boards. For this purpose, a copper-clad laminate with an inner layer conductor pattern t-V is formed, a circuit pattern is formed on the surface of the plate by etching in advance, a hole is bored, a catalyst liquid is applied to the inner wall of the hole, and a catalyst liquid is applied selectively to the inner wall of the hole. irradiate with ultraviolet rays,
We proposed a method for manufacturing a wiring board having a highly precise pattern in which fine lines are formed by forming a catalytic metal layer and a conductor layer by electroless plating. However, in this method, the catalytic metal is precipitated by a photoreduction reaction only on the pore walls that have been irradiated with the phagocytosis, so it is difficult to uniformly irradiate ultraviolet rays on the pores that fit into the irregularities or on the pore walls with a large aspect ratio. There were a few drawbacks.

本発明の目的は、このような従来法の欠点全解法するた
めになさ1したものでりり、板厚の厚い基板に穿設さr
した小孔径内壁に均一の導体mを形成する配嶽板の製造
方法を提供することにめる。
The purpose of the present invention is to solve all of the drawbacks of the conventional method, and it is an object of the present invention to solve all the drawbacks of the conventional method.
The present invention aims to provide a method for manufacturing a mounting plate that forms a uniform conductor m on the inner wall of a small hole.

本%明によnば次の■〜[株]の各工程からなることを
特徴とするスルーホールプリント配緘板の製造方法が得
ら牡る。
According to the present invention, a method for manufacturing a through-hole printed siding board is obtained, which is characterized by comprising the following steps 1 to 1.

■ 鋼張り積層板にエッチジグレジストとなるドライフ
ィルムもしくはレジストインクでパターンを形成しエツ
チングして導体パターンを形成すする工程1 、■ 前記積層板の所望の位置に孔を穿設する工程。
(1) Step 1 of forming a pattern on a steel-clad laminate using a dry film or resist ink serving as an etch resist and etching it to form a conductor pattern; (2) Drilling holes at desired positions in the laminate.

■ 前記槓I−板を増感液に浸漬して表面および孔壁面
に増感層を形成する工程、 [相] 前記積層板の孔會除いた嵌■に紫外線を照射す
る工程。
(2) A step of immersing the laminated board in a sensitizing solution to form a sensitizing layer on the surface and the hole wall surface; [Phase] (2) A step of irradiating the holes of the laminated board with ultraviolet rays.

[株] 前記槓ノー板を活性化液に浸漬して、孔内壁に
触媒金属を析出させる工程。
[Co., Ltd.] A step of immersing the above plate in an activation liquid to deposit catalyst metal on the inner wall of the hole.

[株] 前記積層板を無電解めっき液に浸漬して、孔壁
面に導体層を設ける工程。
[Co., Ltd.] A step of immersing the laminate in an electroless plating solution to provide a conductor layer on the hole wall surface.

以下率5811’t”第1図に基づいて説明する。This will be explained based on FIG. 1.

第1図(5)は内層に導体パターンを有する多層積層板
(以下、積層板と略称)lOwTrfI図で601表面
は一銅箔2の層によって一体成型さrしている。
FIG. 1 (5) is a multilayer laminate (hereinafter abbreviated as laminate) lOwTrfI having a conductive pattern on the inner layer, and the surface 601 is integrally molded with a layer of copper foil 2.

この積層板1にドライフィルムめZいはレジストインク
などのような工?チングレジストパターンを被着させた
のち、公知のエツチング方法で銅箔2の所望部分以外を
除去して辰圓に4体回路パターン(以下回路)ゝターン
と略称)2aを形成する(第1図(均)。
Is there a dry film or resist ink applied to this laminate 1? After the etching resist pattern is applied, the copper foil 2 is removed from the desired portions using a known etching method to form a four-body circuit pattern (hereinafter referred to as "circuit turn") 2a in a dragon circle (see Fig. 1). (Yen).

次に5回路パターン2at−保護するために槓層板lの
表面へ耐めっき性のコーテイング材を塗布して永久的に
残る保護マスク3を形成する(第1図(シ))。
Next, in order to protect the five circuit patterns 2at, a plating-resistant coating material is applied to the surface of the laminate plate 1 to form a permanent protective mask 3 (FIG. 1(B)).

しかる後に、ドリルで積層板lの所望箇所に貫通孔(以
下孔と一6祢)4を穿設する(第1図QJ))。
Thereafter, a through hole (hereinafter referred to as hole) 4 is drilled at a desired location in the laminate l using a drill (FIG. 1 QJ)).

次に1文献フォトイメージングプロセスフォアプリンテ
、ドサーキットマニ7アクチュア−(4’hoto−i
maging process for Pr1nte
d C1rcuitjbnufacture(1,B、
Goldman+P1ating))で知らILるよう
な塩化第1錫の増g液、すなわち塩化第1錫10 g/
L+塩酸1塩酸10シt/lO溶液板lを約2分間浸漬
して、積層板1の表面および孔4の内壁に塩化第1錫か
らなる増感層5を形成する(第1図(1−))。次いで
孔4の内壁のみM元させないで%積層板lの表向f:嬉
光させるために表面に孔ポジフィルム6を蜜漬させたの
ち、上下両面から低圧水銀灯で紫外線を照射する(第1
1忰))。
Next, 1 reference photoimaging process for print, circuit mani 7 actuator (4'hoto-i)
Creating process for Pr1nte
d C1rcuitjbnufacture(1,B,
A thickening solution of stannous chloride, as known from Goldman+Plating), i.e. 10 g of stannous chloride/
A sensitizing layer 5 made of stannous chloride is formed on the surface of the laminate 1 and the inner wall of the pores 4 by immersing the plate in a solution of L+hydrochloric acid 10 t/lO for about 2 minutes (see Fig. 1 (1)). −)). Next, without exposing only the inner walls of the holes 4 to the surface of the laminate 1, a hole positive film 6 was soaked on the surface of the laminate 1 to make it happy, and then ultraviolet rays were irradiated from both the upper and lower surfaces with a low-pressure mercury lamp (the first
1 son)).

′   この工程により表面の塩化第1錫からなる増感
層5のみを酸化して塩化第2錫(8nt’14)層5a
に賦化させる(第1図(Ci )。
' Through this step, only the sensitizing layer 5 made of tin chloride on the surface is oxidized to form the stannic chloride (8nt'14) layer 5a.
(Figure 1 (Ci)).

次に表面に塩化第2一層5aを形成した積層板lを塩化
パラジウム1 g/L+塩酸IQmt/lの活性化溶成
に約2分間浸漬し、孔4の内壁にパラジウムt−還元析
出させる。さらに水洗工程により衣−〇塩化第2錫層5
aを除去し孔内M4のみにバラ、ジウムの触媒金輌層7
を形成する(第1図(へ))。
Next, the laminate 1 having the second chloride layer 5a formed on its surface is immersed in an activating solution of 1 g/L of palladium chloride + IQmt/L of hydrochloric acid for about 2 minutes, so that palladium t-reduction is precipitated on the inner walls of the holes 4. Furthermore, through the water washing process, the coating -〇Stannic chloride layer 5
a is removed and a catalyst gold layer 7 of rose and dium is formed only in the hole M4.
(Fig. 1).

この積層板lをシ、プーレ社製の商品名CP−70のよ
うな厚付は用無電解銅めっき液に浸漬すると、触媒金属
層7が核になって銅の導体層8が孔4の内壁に形成さn
て表mttot−導通させる導体(ロ)路が積層板lに
形成さnる(g1図(1))。
When this laminate l is immersed in an electroless copper plating solution such as CP-70 manufactured by Poulet, the catalytic metal layer 7 becomes a nucleus and the copper conductor layer 8 forms the hole 4. formed on the inner wall
A conductor (b) path is formed in the laminated plate l (Fig. 1 (1)).

以上2本発明により、 (1ン  銅張り積層板の表(3)にめっきすることな
く厚さの定まった銅のみをエツチングするので、従来の
回路幅0.1〜0.1511−公差*0.035mでめ
ったものが、公差*0.0111111で高精度化でき
る。
According to the above two aspects of the present invention, only copper of a fixed thickness is etched without plating on the surface (3) of a 1-inch copper-clad laminate. 0.035m is rare, but with a tolerance of *0.0111111, high precision can be achieved.

(ll)  またQ、1lIs程度の値組線化さnた回
路パターンでも熱因子に十分耐える安定した接着強度が
得らnる。
(ll) Also, even with a circuit pattern having a value set of about Q, 1lIs, stable adhesive strength that can sufficiently withstand thermal factors can be obtained.

(ii)  孔内壁のみに選択的に無′−解銅めっ′#
iを施すので、回路パターンまで無電解銅めっきするフ
ル・アグイティプ法と比べて、析出銅゛の柄費蓋が約1
/10となり大幅なコストダウンになる。
(ii) Selective copper-free plating only on the inner wall of the hole
Compared to the full aguitip method, in which electroless copper plating is applied to the circuit pattern, the handle cost of deposited copper is approximately 1
/10, resulting in a significant cost reduction.

OV)  また、アスづクト比が大きく、孔壁の凹凸が
めっでも欠陥がなく、厚さの均一なめっきが得ら1し品
質の安定化が図ILる。
OV) In addition, the aspect ratio is large, and even if the hole walls are uneven, there are no defects, and plating with a uniform thickness can be obtained, resulting in stable quality.

(V)  エツチド・フォイル法で回路パターンを形成
するので、ア1イティプ法で心安とさiLる核層似茨梱
O粗化エツチングが不要である。したがって、多層板の
内ノー導体層がエツチングさrしることもなく、信90
4度の萬い多J−プリント配線板が得らnる。
(V) Since the circuit pattern is formed by the etched foil method, there is no need for roughening etching similar to the core layer, which can be safely performed using the itip method. Therefore, the non-conductor layer in the multilayer board is not etched and the reliability is 90%.
A printed wiring board of 4 degrees is obtained.

なお1本発明プリント配線板の製造方法はマルチワイヤ
ー配線板の製造プロセスにおいても採用することかでき
るので、高精度化および細断性の見地から特に有効でり
ることは百9までもない。
Note that the method for manufacturing a printed wiring board of the present invention can also be adopted in the manufacturing process of a multi-wire wiring board, so it is not particularly effective from the viewpoint of high precision and shredability.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(へ)〜(1)は本発明のプリント配線板の製造
方法を示す工程図。 l・・・・・・(内1ノーに導体パターンを有した)銅
張り積層板、2・・・・・・表面層の鋼箔、2a・・・
・・・導体回路パターン%3・・・・・・保護マスク、
4・・・・・・孔、5・・団・増感層(塩化第1錫層)
、5a・・・・・・塩化第2錫層。 6・・・・・・孔ポジフィルム、7・旧・・触媒金属層
(パラジウム)、8・・・・・・(無電解銅めっきの)
導体層・第 1 図 2 第1図
FIGS. 1(f) to (1) are process diagrams showing the method for manufacturing a printed wiring board of the present invention. l... Copper-clad laminate (with conductor pattern on 1), 2... Steel foil on surface layer, 2a...
...Conductor circuit pattern %3...Protective mask,
4...hole, 5... group/sensitizing layer (tinn chloride layer)
, 5a...Stannic chloride layer. 6...Positive film, 7...Old catalyst metal layer (palladium), 8...(Electroless copper plating)
Conductor layer・Fig. 1 Fig. 2 Fig. 1

Claims (1)

【特許請求の範囲】 次の各工程を有することt−特徴とするプリント配線板
の製造方法: ■ 銅賊り積層板にエツチングレジストとなるドライフ
ィルムもしくにレジストインクでパターンを形成しエツ
チングして導体バター/を形成する工程。 ■ 前記積層板の所望のに置に孔を設ける工程。 ■ @配積層板を増感液に′&潰して表面および孔−面
に増感層を形成する工程、 ■ 前記積層板の孔を除いた辰−に衆外縁を照射する工
程。 Q 前記積l−板1!−活性化液に浸漬して、孔内縁に
触媒金k14を析出させる工程。 の 前記積層板を無1j91めっき液に浸漬して、孔壁
面に導体層を設ける工程。
[Claims] A method for producing a printed wiring board characterized by having the following steps: ■ Forming a pattern on a copper-etched laminate using a dry film or resist ink serving as an etching resist, and etching it. A process of forming a conductive butter. (2) A step of forming holes at desired positions in the laminate. (2) A step of soaking the laminate in a sensitizing solution to form a sensitizing layer on the surface and the hole surface; (2) A step of irradiating the outer edge of the laminate except for the holes. Q The above product l-board 1! - A step of depositing catalytic gold K14 on the inner edge of the hole by immersing it in an activation liquid. A step of immersing the laminate in a 1j91 plating solution to form a conductor layer on the hole wall surface.
JP14324581A 1981-09-11 1981-09-11 Method of producing printed circuit board Pending JPS5844798A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14324581A JPS5844798A (en) 1981-09-11 1981-09-11 Method of producing printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14324581A JPS5844798A (en) 1981-09-11 1981-09-11 Method of producing printed circuit board

Publications (1)

Publication Number Publication Date
JPS5844798A true JPS5844798A (en) 1983-03-15

Family

ID=15334260

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14324581A Pending JPS5844798A (en) 1981-09-11 1981-09-11 Method of producing printed circuit board

Country Status (1)

Country Link
JP (1) JPS5844798A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05195475A (en) * 1991-11-07 1993-08-03 Beloit Technol Inc Wide nip type web press and method for controlling its pressure profile

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05195475A (en) * 1991-11-07 1993-08-03 Beloit Technol Inc Wide nip type web press and method for controlling its pressure profile

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