JPS5844534A - Parallel-serial converting circuit - Google Patents

Abstract

PURPOSE:To ensure the economical conversion of parallel data into serial data which have continuation between words, by fetching alternately and storing temporarily the parallel data of the prescribed parallel data and then extracting these parallel data in the form of the serial data alternately and with each prescribed word. CONSTITUTION:The clocks CLOCK applied to a clock counting part 10 are counted with each prescribed number within the part 10. Based on this count result, the prescribed word length discriminating signals Q1 and Q0 are produced and fed to a status information converting part 20 and a serial data output part 50. The information Q1 and Q0 are converted into the status information of a prescribed length at the part 20 to be fed to a microprocessor MPU. Thus the MPU transmits the chip selection signal to a data buffer part 30 or 40 and stores temporarily the parallel data D0-D7 and D8-D15 of prescribed word length in the shift registers 31 and 32 or 41 and 42. The part 50 extracts the parallel data stored in the registers 31, 32, 41 and 42 with each prescribed word length on the basis on the signals Q1 and Q0 and feeds these data in the form of the serial data DATA which have no intermittence between words.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides nine consecutive parallel data sessions of a predetermined word length.
The present invention relates to a parallel/serial conversion circuit for converting aj into continuous serial data without interruption.

For example, it may be necessary to output serial data from a microprocessor to an external device as shown above.
Since the time occupied by the microprocessor for data transmission must be extremely small, the microprocessor must be designed so that it only needs to output the corresponding parallel data every time it is needed.

However, it cannot be said that such parallel/serial conversion circuits have been sufficiently developed and maintained as peripheral circuits for microprocessors, especially 16-bit ones.

An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and to provide an economical parallel/serial conversion capable of converting continuous parallel data of a predetermined word length into corresponding serial data with continuous word spacing. The purpose is to provide circuits.

The feature of the present invention is to capture and count a predetermined clock,
A clock counting section generates predetermined word length identification information according to the counting result, and a status information converter 41 converts the word length discrimination information into predetermined status information and sends it to the data bus by a corresponding chip select signal. a pair of data buffer sections that alternately capture and temporarily store parallel data of a predetermined word length from the data bus in response to a corresponding chip select signal; The parallel/serial conversion circuit includes a serial data output section that alternately extracts and sends out the accumulated parallel data as serial data every predetermined word length.

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram of an embodiment of a parallel/serial conversion circuit according to the present invention, and FIG. 2 is a time chart thereof.

Here, 10 is a clock counting section, 11 is an OR gate thereof, 12.13 is a same/parter, 14.15 is a same/toge), 16.17 is a same Nantes gate, and 18 is a The output Qt-cuffs to be sent every predetermined number of stitches (for example, 8) of the clock CLOCKO, 19, is the counter 18.
20 is a status information converter, 21 is a decoder thereof, 22 is a passdraino (, 30, 40 are
The data buffer units 31, 32, 41, and 42 temporarily store the parallel data in the shift register (for example, 8 bits) from bits A to HK, and sequentially send it out as serial data from output terminal 0. , a serial data output section; 51 is a selector for the serial data DATA; 52 is a selector for the clock CLOCK;
60 is a chip select signal relay section, 61, 62.63
is the or gate.

First, when the parallel/serial conversion operation in this circuit is started, the initial setting signal ICL is input from the microprocessor MPU or the external device tEXT to the clock counting section 10, and the initial setting (clearing) of the counter 18 and 19 is performed. be exposed.

After that, when the chip select signal COD and memory write signal MW (both low level signals) are sent from the microprocessor MPυ, the chip select signal relay section 6G
or game) 61 through data buffer 7 parts 30 glue 7
The registers 31 and 32 are driven, and a predetermined word length (for example, 16
Parallel data DO-D15 of the pit) is transferred and stored via the data bus.

Next, one clock CLOCK (which may be supplied from an external device EXT, microprocessor MPU, or any other source) is a clock! OR gate 11 with rl' number 410. The output Q is counted by the counter 1B through 81- of the clock CLOCK (i.e., CL
OCK 8, 16, 24, 32. . . . corresponding to K) is sent out.

p1 inverter 12. Since the output Q of the AND gate 14Fi is applied to the clear terminal CL of the counter through the Nants gate 16, the clock count when the counter 18 is in the clear state (for example, the clock CLOCK
This is to ensure that the stitches can be completed with ease.

The output QFi is inverted by the inverter 13, and the counter 19 changes the outputs Q and Q・ at the falling edge of the inverter 13.
CLOCK (7) 8 pieces and K, +1st order, “oo”
@Q1m, ""10", '11", and repeat this. Furthermore, clearing every 4 counts is the output Q,
From the state of Q (for example, "11"), K is passed through the Nantes gate 17.AND gate 1st-.

This output Qs Qe becomes word length identification information and is input to the status information converter 0 and the clear data output unit 50.

In the serial data output section 50, this information is sent to the selector 5.
1 and 52 switching control terminals A and BK are applied, and its serial data output terminal 88t and clock input terminal 8B are
According to the above information, the input terminals are connected to the output terminals YO to Y3 as shown in the following table.

Further, each of the selection terminals YO to Y3 is connected to the output terminals 0 to 77 of the 77 registers 31.32 and 41.42 of the data buffer section 30.40, respectively, as shown in the following table. Connected to clock terminal CK.

Therefore, shift register 31.32 or 41.4
The 16-bit word length parallel data stored at 24C is stored at the desired clock speed (i.e. clock CLO
CK), 1@Next, 7 real data DATA1
From the shift register 31 as 01 to 108, 109
~116 from the shift register 32, 201~2
08 from the shift register 41, 209 to 216
It will be sent out from the shift register 42 as a.

Note that the shift registers 31, 32, 41.42 each have 8
Although a general-purpose bit type is used, if a 16-bit type is used, it is sufficient to provide one for each data buffer section 30 and 40, and two for each of the selectors 51 and 52. The selected terminal may be used.

On the other hand, the status information converter 20 takes in the above-mentioned chain length identification information, decodes it with the decoder 21,
Decode outputs XO to X3- are obtained according to the word length identification information.

Chip select signal Ca from microprocessor MPU
F. When the memory write signal MW (all low level signals) is sent out, the path driver 22 of the status information conversion section 20 is driven through the OR gate 63 of the chip select signal relay section 60, and the decoded output is sent to the data bus. D
The status information of the parallel/serial conversion operation in this circuit is read and identified by the microprocessor MPU.

As a result, the microprocessor MPU outputs the chip select signal C8D and CUg (
Both are low level signals, and the memory write signal M
Wt-accompanying) gold, when the status is (for example, decoder output "xO~x3" = "0111" or "11"
01”), the data buffer unit 30 or 4
0 shift register 31.32 or 41.42 to 16
Parallel data of bit length can be stored alternately.

In this way, as long as the parallel data is stored alternately in the data buffer sections 30 and 40 from the microprocessor MPU, the clock CLOCK is
9 serial data DA with K synchronization and continuous word spacing.
TA f: Can be converted and sent.

Note that the initial setting for data transfer is, for example, to set constant pattern data t- as an initial value in the data buffer section 30.40.
By writing this gold serial data DAT
The external device DJ that received the data as A identifies the specific pattern and prepares to accept subsequent data transfer. The end of data transfer can also be similarly identified by a specific pattern.

In the above description, the microprocessor MPU can perform other processing operations other than when transferring parallel data, so there is no risk of its efficiency decreasing.

As explained in detail above, according to the present invention, a general-purpose I
C (semiconductor integrated circuit) Parallel/serial conversion circuit t- using gold, related to serial data with continuous word spacing
Since it can be realized economically, its effects are significant, such as expansion of peripheral circuits of microprocessors.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a parallel/serial conversion circuit according to the present invention, and FIG. 2 is a time chart thereof.

Claims (1)

[Claims] 1. A clock hand unit that inputs and counts a predetermined clock and generates predetermined word length identification information according to the counting result, and a corresponding chip that converts the candy length identification information into predetermined status information. a status information conversion unit that sends out to the data bus in response to a select signal; a pair of data buffer units that alternately captures and temporarily stores parallel data of a predetermined word length from the data bus in response to a corresponding chip select signal; and the word length identification information. and a serial data output section which alternately extracts and sends out the optical parallel data temporarily stored in the data buffer section according to a clock as serial data every predetermined word length.