SU1633377A1 - Device for programmed controlling production processes - Google Patents

Abstract

The invention relates to automation and computing and can be used in automated systems for software control of technological processes, for example, in computer numerical control systems. The purpose of the invention is to expand the field of application of the device. The goal is achieved by the fact that a known device, containing a control unit, a clock generator, a controller, a bus address driver, a memory address decoder, fixed and main memory blocks, a bus memory driver, an address / address decoder, a group of bus drivers for I / O devices, the first to third elements of OR, the first to fourth elements of AND, the first register of the branch address, the comparison block, the trigger, and the bus driver of the branch, are additionally entered. branching address register, the register group multippeksor group blgkov comparison, the AND groups- and trigger counter. The introduction of new elements makes it possible to significantly reduce the amount of memory of the multi-alternative branching and expand the scope of application of the device by introducing discipline. nor is the normal coding of the members of a perfect disjunctive normal realizable system of Boolean functions or codes of branch branch rank variants: n, where n is the size of the logical conditions being processed. 3 ill., 4 tab. SS (Л о со со со i i

Description

The invention relates to automation and computing and can be used in automated systems for software control of technological processes, for example, in computer numerical control systems.

The purpose of the invention is to expand the field of application of the device.

The essence of the invention is to reduce the amount of memory of multi-alternative branching and expand the field of application of the device by introducing the discipline of pre-coding members of a perfect disjunctive normal form (SDNF) of the implemented system of Boolean functions or variant codes.

branching of ranks n, where n is the width of the logical conditions being processed.

The essence of the new discipline is to enter members' information into the group of registers. SD1N (subordinates of PDNF), variant codes (part of variant codes) branching during initialization, or when reconfiguring the device1, comparing this information with information on the group of senior bits of logical conditions and generating an identification signal of one of the comparison circuits of the comparison circuits group, or such a signal is generated; in the formation at the output of a group of elements And with three states at the output of an information identification code, or a single identification code, in the implementation of a multi-alternative branching discipline similar to the known one, with some part of the bits (lower bits) of logical conditions through a multiplexer directly leads to memory addressing, and the other part (most significant bits), subjected to pre-coding, addresses memory indirectly, in accordance with the assigned group of senior inputs x address branching codes.

FIG. 1 is a functional diagram of a software process control device; FIG. 2 is a timing diagram for outputting information to the registers and a group of registers in the initialization or tuning mode of FIG. 3 is a timing diagram for issuing the second and third bytes to the system data bus in a multi-branching mode with pre-coding. ,

A device for software control of technological processes (Fig. 1) contains a control unit 1 containing outputs 1 addresses, outputs data inputs 12, control outputs 1j, clock inputs of the first 1 and second phases 1 synchronization, reset input 1g, readiness input 17, output 1 1 synchronization, clock generator 2, containing input 2 (synchronization, outputs of the first 2g and second phases 2j of synchronization, output 2 of reset, output 25 of readiness, output 2g of synchronization, controller 3, containing outputs-inputs 3 of data, which are the data bus outputs 3 controls a control bus,

bus driver 4 addresses containing the outputs of the bus address addresses, the decoder 5 memory addresses containing outputs connect the permanent memory 5, and RAM 5, block 6 of the program permanent memory, block 7 of the program memory during operation , bus driver 8 RAM, decoder 9 addresses of input devices 5 output, containing a group of outputs 9, connecting external devices. Outputs 9g and 9z, a group of bus formers 10 for left-side devices, the first 11 and second 12 elements OR, the bus driver shaper 13 for branching, trigger 14 for branching, the first 15, second 16, third 17 and fourth 18 And elements, first 19 and second 20 branch address registers, group m registers

5 21 | -21t, where m is the number of members of the PDNF describing branching conditions, comparison block 22, multiplexer 23, group of comparison blocks, AND 25-25 group of elements with three states at the output, counting trigger 26, third element OR 27 , readiness input 28, capture input 29, interrupt request input 30, sleep output 31, interrupt enable output 32, group 5 PU inputs 33c-33m of the oldest branch addresses, group 34 of higher-order logical conditions, group of 35 lower-order logical conditions, information outputs 36, information inputs 37, reset input 38, control inputs detection, a first group of inputs 40, a second group 41 of inputs.

The control unit 1 is designed to control the system and solve numerical problems. It can be implemented, for example, on a standard integrated circuit IC KR 580 IR 80A. The matching of the input-output unit 1 and this chip can be pre50

put table.1.

The clock generator 2 is designed to generate synchronization signals. The correspondence of the inputs-outputs of the generator 2 and this chip is presented in table 2.

Input 13 and outputs 9 of the KR 580 GF24 chip are not activated.,

The controller 3 is designed to form a control bus and to organize bidirectional data transmission over the data bus 3.

The correspondence of the inputs-outputs of this chip and the inputs-outputs of the controller 3 can be represented by table 3.

the inputs of the tire driver RAM and from its inputs / outputs to the bus 3, the system data.

Record in memory

In this case, only the first input of the resolution of the bus driver is activated. Data from the bus 3 | system data is sent to its inputs and outputs,

The bus driver 4 addresses pre-jg and from the outputs to the data inputs of block 7

assigned to increase the load capacity of the bus 4 (addresses and to disconnect its inputs / outputs from it by transferring them to high-impedance states on the signal Confirm capture that goes to its first and second enable inputs from control unit 1.

Bus driver 4 addresses can be implemented, for example, on standard integrated circuits 589 AP16.

The correspondence of the inputs-outputs of the block 4 and the inputs-outputs of this chip can be represented by table 4.

Outputs 2, 5, 11, 14 are not used.

Decoder 5 memory address is designed to decrypt the information on the bus 4 | addresses by the permitting engine at its first control input, if the second one is inactive, and generating crimping sampling signals for connecting blocks of constant n or 7 operational memory.

Fixed memory block 6 is labeled for long-term programming programs and data. Block 7 of the opera-tion memory is designed for memory programs, data and for recording them only during operation of the device, as well as for organizing the stack.

The operating mode of the RAM block 7 is determined by the combination of the enable signal and the write signal.

Tire driver 8 RAM designed to increase the load capacity of the tire 3 | data of the system and for the organization of the connection to it of the inputs and outputs of the block 7 of the RAM, depending on the control signals in the various modes.

Reading memory.

At the same time, the first and second inputs of the bus driver 8 are activated. The data from the outputs of the RAM block 7 is fed to

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operative memory,

The decoder 9 addresses of I / O devices is intended to e) decrypt the address information on the 4 address bus on the system address bus to connect to the bus 3 data to connect to the bus 3 i data of the corresponding input-output I / O bus 10 to control elements And 17 and 16.

The I / O bus drivers 10 are designed to increase the load capacity of the bus 3 / system data, for entering data from the information inputs 37, while allowing both inputs of one of the bus I / O drivers 10 that are activated by the decoder 9 I / O devices are activated. , g also for outputting data from block 1 of the control unit; Lemi on informational outputs,: 36. When the j-th first permissive input of one of the smart formers 10 of the output signal is activated, the output of the ds-cipher text is 9 addresses of the mouth roist in vyoda- g lshda.

The first element 11THI 1 1 is designed to generate an enable signal i-a control pitch children 5 address memory i, if the control bus b q has one of the signals Read memory, Write to memory.

The second element OR 12 is designed to generate a signal for the decoder 9 addresses of I / O devices, if on the control band K there is one of the signals output to output device, input from the device.

Tire shaper 13 branching designed to increase the load capacity of the tire 3 | data and connecting to it the signals from the output of multiplexer 23 when activating its enable input. Otherwise, the outputs of the tire former 13 are in high impedance

state and do not affect the operation of data bus 3.

The branch trigger 14 is designed to receive from the bus 3 single programming bit data on the leading edge of the pulse at the output of the AND 16 element in order to enable the multi-alternative branching mode by activating the first input of the AND 15 element. When receiving the zero bit, the mode is prohibited.

The first element And 15 is designed to control the bus driver

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formations of members (subordinates) of SLNF implemented boolean functions or variant codes (parts of codes) of the branch from the outputs of the second register 20 of the branch address of the signals from the output of the And 17 element. In each subsequent register of registers 20, 21, -21t the information is recorded from the output of the previous one with reduce hardware costs so that for t + 2 cycles of information output by control unit 1 at the address of the output port, exciting output 9h of decoder 9, element 17

ten

13 branches in multialtern mode- 15 in registers 19 and 20 of the group

signal branching Read control memory b of the control bus if the trigger of branch 14 is set and the output of the element OR 27 is excited.

The second element 16 is intended to form a synchronization pulse of branch trigger 14, if the output 92 of the decoder addresses the I / O devices and / or the discharge is driven Output to the bus control device Zg of control.

The third element And 17 is designed to control the recording of information in registers 19, 20 and 21, - 21 m in that case

25

The required information is recorded (FIG. 2).

Comparison unit 22 is designed to determine the branch point by comparing information on bus 4 (and res and the outputs of registers 19 and 20 of the initialization of multi-branch branch mode. The output of circuit 22 is triggered when the address set on the address bus 4 matches the address of the second byte of the command branching recorded in regs 19 and 20.

Multiplexer 23 is designed

In addition, if the output of $ 9 is decrypted, 30 For connection to the information

torus 9 and bit Output to the output device bus 32 control.

The fourth element AND 18 is designed to control the element OR 27 at its first input if the output of the comparison unit 22 and the discharge is excited. The output of the control outputs 13 of the control unit 1 is excited. The output of the fourth element And 18 is excited by reading the first byte of the branch instruction.

The first branch address register 19 is used to record and store the lower half-address of the program branch point (the second byte address of the branch command) from the bus 3 with a signal from the output of the And 17 element. The first branch address register 19 broadcasts information to the inputs of the second branch address register 20. The latter is intended for recording and storing the higher half-address of the branch point of the program of the outputs of the first register 20 of the branch according to signals from the output of element 17. The second register 20 of the branch address transmits information to the inputs of a group of registers 21-21.

The group m of registers 21p is intended for recording and storing in35

40

inputs of the bus driver 13 in either the concatenation of inputs 3 and 41 of the device, or the concatenation of inputs 40 and the combined outputs of the AND 25-25 elements with three output states to form the second and third bytes of the branch instruction, depending on the logical conditions 35 and 34 .

The group of blocks 24–24m of comparison is intended to identify h (subordinates of the PDNF), option codes (parts of codes) recorded in group m of registers 21, “–21 on the discrete inputs of group 34 of high-order logic conditions. No more than one exit of the reference unit block is always required.

The group of elements AND t by the output states is intended to form an identification code for information corresponding to the 33 I-33t branch address of the same name that is the highest branch address if the output of the corresponding block 24, -24m comparison from the link and the corresponding control input are excited laziness - from inputs 39i-39n). In particular, when the outputs are excited, the block

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The required information is recorded (FIG. 2).

Comparison unit 22 is designed to determine the branch point by comparing information on bus 4 (addresses and outputs of registers 19 and 20 to initialize the multi-alternative branch mode. The output of comparison circuit 22 is excited when the address set on the address bus 4 matches the address of the second byte of the branch command, recorded in registers 19 and 20.

Multiplexer 23 is designed

To connect to information

the inputs of the bus driver 13 branching or the concatenation of the inputs 35 and 41 of the device, or the concatenation of the inputs 40 and the combined outputs of the AND 25-25 elements of the three output states to form the second and third bytes of the branch instruction, depending on the logical conditions 35 and 34.

The group of 24–24m comparisons is intended to identify members (subordinates of the PDNF), branching codes (parts of codes) recorded in group m of registers 21, “–21 on the discrete inputs of group 34 of the high-order logic bits. No more than one output of the comparison block bodies is always excited.

The group of elements and the three output states are used to form an identification code for information corresponding to the higher branch address set on the same input group 33, -33t of the highest branch addresses if the output of the corresponding block 24, -24m comparison from the group and the corresponding control input are excited inputs 39i-39n). In particular, when the outputs of the block are excited

24 ,, - 24 comparisons of the group at the combined outputs of the group of elements AND 25, -25 and three codes can be set in three states (preset at the inputs 33c-33), the weights of which correspond to the number of the comparison block, counting from zero, a group of blocks 241-24tnc excited output (O, 1.2 ... t-1). The width of the outputs of a group of elements is equal to the value of intlop, 2 (go + 1), where int is the nearest larger integer.

1 If the output is not excited at one of the blocks 24, -24 tons of group comparison, the output outputs of the group of elements are And 25 (-25yn is in a high-impedance state, which is perceived by the corresponding input of the multiplexer 23 as in TTL logic - logical 1.

The counting trigger 26 is designed to control the multiplexer 23 on the signals from the output of the element 15. When the control unit 1 reads the first byte of a branch command (i.e., a transition command having a three-byte structure, for example, the IMP, CALL, LDA, etc. commands for the microprocessor 580 ) the counting trigger 26 is reset to initial reset. The address of the second baptl of such a command is branching deshi reruy; block 22 comparison. The impulse of h-: the second byte on its rear frame from the output of the AND 15 element remembers the counting trigger 26, providing switching of the multiplexer 23 and controlling the element AND 15 through the element OR 27, which is necessary. to switch the third byte through the bus driver 13, because the address. The third byte is not decrypted by block 22. At the end of the read pulse of the third byte, trigger 26 is zeroed.

The third element OR 27 is designed to control the element 15 by its third input either by the signal from the output of element 18 and 18 (reading the second byte of the branch command) or by the signal from the output of the counting trigger 26 (reading the third byte of the event command).

The readiness input 28 is intended for receiving an external readiness signal, for example, from external slow-acting drives. The capture input is leverage to receive an external signal

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grip, for example, in external high-speed drives.

The interrupt request input 30 is intended to receive an external interrupt signal, for example, in the event of a power failure.

The wait output 31 is designed to generate a wait signal that is a response to unexcited readiness input 28.

The interrupt enable output 32 is configured to generate an interrupt enable signal from the internal trigger of the control unit 1. The group of inputs 33 ,, -33 tons of higher branch addresses is intended to form the member identification code (connected) of the PDNF of the implementing system of Boolean functions or the code (part of the code) of the branch variant on the combined outputs of the And 25 /) elements - 25rt. The information on the inputs 33c-33 can be set rigidly by soldering (connecting to the Plus buses, Minus the power source via the limiting resistors) or softly from the outputs of the registers, which can also be programmed by the control unit 1 with the help of technical means - nyu to uetroyst y.

BKHODMP t lvna intlog 4U,

A group of 34 gtrp / bits of logical conditions is intended to connect the optima of the lower part of the aeration of the multiplier to ;;, the conditions to the first, or to the groups of inputs of blocks 2 (-24 ,, comparison). Logical conditions - ..t be both external, i.e., the state of discrete d; m I1: ol technological process, and internal - obtained in the result of the operation of control unit 1 to the registers, for example, to obtain later automaton mappings.

Group 35 of logic bits of logical conditions is intended to receive the corresponding part of the logical conditions discharge, which may be the same as described. The information on inputs 34 and 35 is changed at such intervals that the control unit 1 manages to process it any and all views.

Information outputs 36 are intended for issuing control aircrafts

actions on executive bodies to control the technological process, including the results of multi-alternative branching.

Information inputs 37 are designed to receive information about the state of the process sensors, which is processed in the usual way.

The reset input 38 is designed to receive an external system initial reset signal.

The control inputs 39, -39T are designed to control a group of I elements. When processing the PDNF members (subordinates), codes (parts of codes) of branching variants, the number of which differs from the maximum number of hectares, logical Os are fed to the inputs 39d-39t by the corresponding unused element from the groups of 241-24t elements in order to eliminate false identification codes.

The first group of inputs 40 is intended to form, together with information at the outputs, a group of elements AND a full bit code equal to the data bus 34 width.

The second group of inputs 41 is intended to form, together with the information at the inputs of bits 35, the full code of the data bus width. If R is the data bus width, R4 (, RH R49 is the width of the corresponding inputs, then

R,

RVT +

R,

The bus driver 4 addresses are formed by address signals at the corresponding outputs 1 | unit 1 UPCHA 4 ° 62. The device works as follows

Normal mode of operation.

In this mode, the clock 2 (Fig. 1) generates two non-overlapping clock sequences, which from its outputs 2 and 2j arrive at the clock inputs of the first 1f and second 1 phases of the control unit 1.

Control unit 1 generates data and control address signals:

after a reset signal is applied to its corresponding input 1, the external reset signal from system input 38 is gated in clock generator 2t and arrives at its output 24, registers 19, 20, 21, and 21t zero, triggers 14 and 26,

4o + int 1 ° §2. + .. directing bus 4 ,, addresses, providing

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its required load capacity

The device can be switched to the interrupt and capture mode by applying the corresponding signals to the inputs 29 and 30. When switching to the interrupt mode from output 32, the interrupt enable signal is removed. When the device enters the capture mode, a capture confirmation signal is set at the corresponding discharge of the control outputs 1 of the control unit 1, which, via the first and second control inputs, transfers the outputs of the bus driver 4 addresses to a high-impedance state. Also on this signal, the outputs of the controller 3, the outputs 1 of the address, the inputs and outputs 1g of the data of the control unit 1 are transferred to the high-impedance state.

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thirty

20

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35

after setting the level of logic 1 at input 28 of the device readiness, the readiness signal is gated in the clock generator 2 and from its output 2. enters input 1-, the readiness of control unit 1, if the device 28 has a logical O signal , then the output 31 of the device is set to a logical 1 signal, indicating that the control unit 1 is in standby mode.

The control unit 1 outputs a status word to the data bus 12 via a synchronization signal at the corresponding output 1g, incoming input 2 of the clock generator 2 at the first clock of each cycle,. And the clock signal 2 gated from the clock 2 output of the clock generator 2 3, in which the status word of the control block 1 is written from the inputs / outputs 1g of the data of the control block 1. The controller 3 generates a code on the control bus 32 as well as a signal on the status word and the signals at the outputs 1 of the control unit 1, and also generates a code on the data bus 3, ensuring its required load capacity and bi-directionality of data transmission at the input-output 1 of the data of unit 1 management

The bus driver 4 addresses forms the address signals on the respective outputs 1 | block 1 pack bus 4, addresses, providing

its required load capacity.

The device can be switched to the interrupt and capture mode by applying the corresponding signals to the inputs 29 and 30. When switching to the interrupt mode from output 32, the interrupt enable signal is removed. When the device enters the capture mode, a capture confirmation signal is set at the corresponding discharge of the control outputs 1 of the control unit 1, which, via the first and second control inputs, transfers the outputs of the bus driver 4 addresses to a high-impedance state. Also, according to this signal, the outputs of the controller 3, the outputs 1 of the address, the inputs-outputs 1g of the data of the control unit 1 are transferred to the high-impedance state.

Control unit 1 reads and executes the program recorded in block 6 of memory or in block 7 of RAM. In this case, the memory address decoder 5 will decipher the address set on the address bus f, if one of the signals Read memory, Write to memory is set on the control bus Zg, the output of the first element OR 11 and the first enable input of the decoder 5 are activated. the inverse of the resolution input is activated by the output of the element 15. If the bus is on bus 4 (the address of the memory is set to the address of the permanent memory, then the output 51 of the decoder 5 and the first control input of the block 6 of the permanent memory are activated.

If the address of the RAM block 7 is set on the address bus 4, the output 5 of the decoder 5, the control input of the RAM block 7 and the first control input of the bus driver 8 of the RAM, are activated.

The outputs of the fixed memory unit 6 are connected to the bus 3 ,, data, if, apart from the first control input, the second signal control input is activated. Receiving from the corresponding bit of the control outputs 1j of the control unit 1. The data is read from the persistent memory unit 6 to the control unit 1 via the data bus 32 data inputs / outputs of the controller 3 at the data inputs / outputs 12 of the control unit 1 in accordance with the addresses received at its address inputs from the address bus ki.

To read data from memory block 7, in addition to activating its control input, a logical signal O is sent to the record input from the corresponding control bus 32 bit Record to the memory, and the second control input of the bus driver 8 of the main memory block is activated by output outputs 1z control unit 1 control Reception. This puts the memory driver 8 in memory mode, i.e. data transfer from the outputs of the main memory unit 7 to the data bus J is organized. Data is read from memory block 7 to control block 1 via bus 3, data in accordance with the addresses, by

| d

ro 25

30 4Q

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step on its address inputs from the bus 4 addresses.

The control unit 1 can write data to the main memory unit 7, while the bus driver 8 of the main memory, via the second control input, from which the active signal level is removed by the corresponding output of the control outputs 13 of the control unit 1, is transferred to the data input mode of the bus 3 | data. Block 7 of operational memory 7 is connected to the recording input, which is activated by the corresponding bit. The recording in the memory of control bus 32 is transferred to the recording mode. The data from bus 3, data is recorded in the block 7 of the RAM in accordance with the address signals received at its address inputs from the bus 4.1 addresses.

In the absence of active levels of control signals, the outputs of the block 6 of the permanent memory and the outputs-inputs of the bus driver 8 of the RAM are in a high-impedance state and disconnected from the bus 3 of the data.

The device enters data from information inputs 37 or outputs data to information outputs 3. Depressing op Q addresses of the device c) deciphering the address set on the 4 address bus, the RSLI activated its input controlling the output of the second element OR 1 when activated its inputs by one of the signals Input from the input device, Output to the output device on the corresponding bits of the control bus Zg.

The outputs of the decoder 9 addresses I / o devices activate the second input resolution of one of the bus drivers 10 I / o corresponding to the address supplied to the address input of the decoder 9 addresses of I / O devices.

The mode of operation (input or output) of bus I / O drivers 10 is determined by the signal at the second enable inputs, i.e. corresponding to the bit Input from the bus control input device 32. In the input mode, the data from the information inputs 37 is fed to the inputs of the corresponding input / output bus driver Yu, and from its inputs / outputs to the bus 3 data through the controller 3 in

control unit 1 for its inputs-outputs -Ijj, data. .

In the mode of data output from control unit 1 on inputs - outputs 1, data through controller 3, bus 3 (data are sent to inputs $ - outputs of the corresponding bus driver 10 input-output, and from its outputs - to information outputs 36.

In the absence of active levels of control signals, the bus I / O drivers 10 are disconnected from the data bus (in a high-impedance state).

The mode of preparation for branching. In this mode, which can be performed when the device is initialized (when the power is turned on, for example, by the monitor program), if the branch is organized in one place of the program, or before the branch, if it is organized many times in different parts of the program, the address of the branch point is recorded. in two registers 19 and 20, the entry of the analyzed members of the SDNF of the system of Boolean functions, computed during the branching process, into a group of registers, as well as the installation of trigger 14 in a single state.

Moreover, on the input group by hardware, for example, the higher branch addresses are set (for example, by connecting the necessary bits through the limiting resistors to the positive and negative power buses) in accordance with the device’s memory allocation card developed by the designer. Units are set up at the control inputs, the number of which, starting at input 39, is equal to the number of the members of the PDNF in the system of Boolean functions calculated by the branching. In order to calculate another system of Boolean functions, the information in the registers 19, 20, 21, -21m and at the inputs ,,,, 391-39t is changed at another point in the program, and the information change at these inputs can be implemented programmatically using external tuning registers .

To write information to the registers 19, 20, 21h-21t, the control unit 1 organizes the output mode to an external device. When this is excited

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the output 9j of the decoder 9 and, since the control bit Zg of the output is activated to the output device, the output of the element 17 is also excited, therefore the information from the bus 3 (data is written to the register 19). The sync pulse from the output of the element 17 is simultaneously sent to all registers 19, 20, 214-21t, as a result of which the registers 20, 21, and 21t store information from the outputs of previous registers: register 20 - from the output of register 19, register 21i - from the output of register 20, etc. All these registers are pre-zeroed by output 2, resetting the clock generator 2, just as k and triggers 14 and 26.

When the output 9 of the decoder 9 is next excited (the control unit 1, writing information to the registers 19, 20, 21-21, accesses the output device at the same address, which drives the output 9 of the decoder 9 tons + 2 times) information from the bus 3 data is recorded in register 19, and from register 19 with the same impulse from element I 17 output - into register 20. At the end of the t + 2 information output cycles in registers 19, 20, 211-21gmv registers 21, -21m are recorded m members of the PDNF system of Boolean functions computed during the branching process, and in registers 19 and 20 the junior and senior half-addresses t program branch points.

The process of moving information in registers 19, 20 is shown in FIG. 2.

Next, the control unit outputs information to the address of the trigger 14, referring to it as an output device with a fixed address. This causes the output 9 of the decoder 9, discharges the control bus Output to the output device, therefore, the output of the And 16 element is excited, A gate at the output of which from the data pins the information bits (in this case, the units) is written to the 1D trigger, which is set to one and activates its output.

Multi-branching mode.

This mode, when the control unit 1 needs to process the information on inputs 34 and 35, it can do this, for example, with a special subroutine. In this case, the comparison circuit 22 decrypts the address of the second

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17

command byte (for example, unconditional branch or call of IMP and CALL subprograms for microprocessor 580). The output of the comparison circuit 22 is activated. If at the same time the discharge of the outputs C of the control unit 1 of the reception control is activated, the output of the element 18 is activated, which through the element OR 27 activates the third input of the element 15. The first input of this element by this time is activated by the discharge of the read control bus 32, and the second the input — the output of the trigger 14 set at initialization. Therefore, the bus driver 13 is opened, the decoder 5 of the memory address is blocked by the inverse of the enable input. Since the output of the trigger 26 is zero (the trigger 26 is reset by system reset from the output 2 of the clock oscillator 2), the output of the multiplexer 23 receives information from the group of 35 low-order bits of the logical conditions that are read into the block 1 through the bus driver 13 control and is perceived as the low byte of a command (unconditional branch or subroutine call).

At the end of the read pulse from the corresponding bit of the control of the falling edge L of the output of the element 15, the trigger 26 is set and activates through the element OR 27 the third input of the element 11 and also activates the address type 23, which transmits information on its outputs to its outputs a group of elements And 25 (-25p, with trm output states, ia which sets the code of the number of the SD member of the computed system of Boolean functions if the information at the inputs of the group 24 of the highest bits of the logical conditions coincides with the information in one of the registers of the 21d-21t group and a single code otherwise (since the outputs of all elements AND of the group of elements of I 25 (-25ts with three states on the exhaust) are in a high-impedance state, which is equivalent in TTL logic feeds to the corresponding multiplexer inputs 23 logical 1).

At the inputs it is installed (when scaling the system from an external register or by connecting the corresponding bits through the limiter

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power resistors to the positive or negative poles of the power source) the code of the bits of the addresses of the memory cells (blocks 6 or 7) so that in concatenation with information from the outputs of a group of elements And 25, -25m with three states at the output of multiplexer 23 the semi-address of the branch address, taking into account the number of addresses required to form commands for issuing the appropriate control actions.

Therefore, the next time the memory is read by the control unit 1 (reading the second byte of the unconditional jump instruction or subroutine call), the read of the control bus 3 is activated again. However, the output of the comparator unit 22 is inactive, since in this case the address is on the bus. The address is set to one greater than the previous one, the output of element AND 18 is not activated. But, since trigger 26 is set, the third input of element 15 is activated through element OR 27, the output of which is triggered and through the driver 13

and h tire

1 dchnh transmitted described

on the information from the multiplex

about rr

1 I

ia / uiHN front of the pulse

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The code; .-: His-mi, And 5, and e trng-ier 26 and HI MuptipAxor 23 understand all the information from LoDon 35.

Vyhg, -1H 1-m.p.); opt 13 transnod vn, (co-signed i -stand, and HI p: ny; on irnny 3 data. removed. (oprp tpgl det iftrt ra 5 memory addresses. Hnoi-1 y equals, received com-1 schu, BJ troy and tu r: bait (ht & swarm and third words r oshm) which depends on the information on inputs 1G; g 34, switches to the appropriate program or subprogram depending on the logical conditions, controlling influences, influence them on the executive bodies from the emperors 36 If it is necessary to do this, discipline mygoodgrnpvnp (branching program control unit 1 AMM1 zeroes the trigger 14, outputting the logical data to it via the data bus. Thus, in addition to and.) The memory size necessary for organizing a response to logical conditions in the process of multiple alternative branching has only partially

The exponential dependence on the number of logical conditions p. The part of the bits of the logical conditions k, which is connected to inputs 35, addresses 2k bits, where a is the length of the segment necessary for generating control signals, rounded to the nearest greater degree of 2. A part of bits (nh) with the help of a group of comparison blocks, a group of elements 25 and 25, with three states at the output, inputs, is encoded so that the number of the combination at the output of multiplexer 23 when its address input is excited is significantly is less than 2nd, and is equal to the value of m + 1, where m is the number of members of the PDNF calculated by the method of multi-alternative branching of a system of Boolean functions.

Claims (1)

Invention Formula A device for software control of technological processes, comprising a control unit, a clock generator, a controller, a bus address driver, a memory ad-JQ decoder, program memory and program memory blocks during operation, a bus memory generator TI, decoder addresses of input-35 output devices, a group of bus drivers of input-output devices, first, second and third elements OR, first, second, third and fourth elements AND, first register address branching, TO block compared No, the trigger and bus branch forwarder, the inputs-outputs of which are connected to the data bus of the device formed by the information outputs-inputs of the controller, g5 the outputs of which are the control bus of the device, the bits of which read memory and write to memory are connected to the inputs of the first element OR-, the output of which connects the CQ pins to the first direct input of the resolution of the memory address decoder, the first output of which is connected to the first input of the resolution of the program memory block, the outputs of which are connected to the data bus the units, the outputs of the first and second phases of synchronization and the output of readiness of the clock generator are connected respectively Q 5 0 five / JQ 35 TO d5 CQ with clock inputs of the first and second synchronization fates and with the ready input of the control unit, the reset output of the clock generator is connected to the reset inputs of the first register of the branch address, branch trigger and control unit, the synchronization output of which is connected to the clock synchronization input of which the ready and reset inputs are the ready and reset inputs of the device, the clock synchronization output is connected to the controller clock input, the information inputs / outputs of which are connected to you The inputs are the control unit whose address outputs are connected to the information inputs of the bus address generator, the outputs of which form the address bus of the device and connected to the information inputs of the memory address decoder, to the address inputs of the program memory block and the program memory block during operation and with the information inputs of the address decoder of input / output devices, each bit of the output group of which is connected to the first permission input of the corresponding bus driver The group I / O capabilities, the interception and interrupt request inputs, the control unit interrupt standby and enable outputs are respectively the device interception and interrupt request inputs and the device interrupt standby and enable outputs, the control output group of the control unit is connected to the control input group of the controller, bit Confirmation of the capture of the group of control outputs of the control unit is connected to the first and second control inverse inputs of the bus address address generator, bit The control outputs of the control unit are connected to the first input of the fourth element I and to the second inputs of the permanent and main memory inputs, the second output of the memory address decoder is connected to the first input of the bus RAM driver and the input of the main memory unit programs during operation, the outputs of which are connected to the inputs of the bus driver RAM, the outputs / inputs of which are connected to the data bus of the device, the outputs of the bus driver RAM These are connected to the information inputs of the program memory block during operation, the control bus bits. The input from the input device and the Output to the output device are connected to the inputs of the second OR element, the output of which is connected to the resolution input of the I / O address decoder. the control output of which is connected to the first input of the second element I, the output of which is connected to the synchronous input of the branch trigger, the output of which is connected to the first input of the first element And, the output of which is connected to the permission input neither the bus branch driver and the second inverse of the address resolution of the memory address decoder, the information inputs of the address decoder of the I / O devices are connected to the address bus, and its second control output is connected to the first input of the third And element whose output is connected to the recording input the first register of the branch address, the industrial inputs of which are connected to the data bus, and the outputs to the higher bits of the second group of information inputs of the comparison unit, the first group of information inputs to the South U is connected to the address busbar, and the output is connected to the second input of the fourth element I, whose output from the furnace is not connected to the first input of the third OR, the output of which is connected to the cold input of the first element AND, the outputs-inputs of the bus driver devices I / O is connected to a data bus, the information inputs and outputs of which are information inputs and outputs of the device, the control bus bit Output to the output device is connected to the second inputs of the second and third elements, And management connected to the second inputs of the resolution of the bus drivers of the device ids-nyv yes and groups, bit Record in the control bus memory is connected to the write input of the pptgram RAM memory unit during operation, discharge Read the control bus memory is connected With the third input of the first element And, the lower bit of the data bus is connected to the information input of the branch trigger, characterized in that, in order to expand the field of application of the device, a second branch address register, a group of registers, a multiplexer, a group of comparison blocks, a group, is entered into it. And elements and the counting trigger, the output of which is connected to the second input of the third element OR and to the address input of the multiplexer, the outputs of which are connected to the information inputs of the bus Branch Former, reset output clock the generator is connected to the reset inputs of the counting trigger, the second register of the branch address and the group registers, the outputs of the first register of the branch address are connected to the information inputs of the second register of the branch address, the outputs of which are connected to the lower bits of the second group of information inputs, and The inputs of the pospeluoschggogo register of the group are connected by informative outputs of the trajectory 1 of the register of i h niloty rep. throne Gruppn L (CDIARNL SOI-GCHRTCH GONNR WITH TYPE R-MI FRUIT WTf vnilhl, the first 1 are the second ones. putao 1 senior rf f-voH n P; h, chchkih V..UH. uggrotigl, a bMx; v i. e, ins v-I with: - vetsgpen;) from ashes. who y n them in the mi leM .HiuH And, rtgry upra mce in. “. l of RVLAR; SYa entrances control / construction, i now-: .ori ,, i eOfeiH ieHbi g. adshmni iffti vtorgl yy / ppa n-ultippa ch-op, the older ones of the second group of the input group of which are ncc ps-pth group HV of one of the cops of the razngpi, junior and senior bits of the pgrroy group of the entrances of the ltiteggrgr, and n - with a group of entrances of mthldshih rlcr:; s lggichekil syllable; 11 devices, two second groups of groups. p codes of the size, rpvnpa rkholop t: (mengstch And groups of groups of groups of branches of the branch of the device, the turn of the third ETRMGNTL And connected to the inputs of the record of the second register of the branch of the branch and re-Utro group, output than i is i connected to the count; m input of a counting trigger 23 findings 589 AP16 A, 7,9,12 1633377 24 Table 153.6, 10.13 1 4- G t 21 t / g / D G. 1h L  i „J g ir  / g  B | c. Xi i; j J 39, mr 2 /. / 77 1-T1 59t Fig 1 neptoio code shared by CSHQ) f-bsh faii t ti connection, faonup  byte read the zth give me a connection ti, faonupaSxa S  byte 2-iauft read the zth give me a