JPS59151231A - Selective reception system - Google Patents

Abstract

PURPOSE:To reduce the load of a transmission controller and to improve the buffer use efficiency, by providing a means which discriminates whether reception of receiving data is required or not and receiving data selectively for a time proportional to the data transmission speed. CONSTITUTION:Information indicating whether receiving data is required or not is written preliminarily in a storage device 108 of a selective receiving circuit 100. When a signal FD which detects a flag in data is inputted in the case of reception, a receiving clock RC is inputted to a counter 103 through an FF101 and etc. When the count value of the circuit 103 becomes 9, the output of an AND circuit 116 is inputted to the device 108 and etc., and the FF101 is reset to stop the supply of the clock RC. Then, a bus switch 107 selects the output of a shift register 106, and a bus switch 109 selects a signal line to a latch circuit 110. Consequently, contents of the circuit 106 are inputted as an address signal of the device 108. By this selective reception, the load of the transmission controller is reduced, and the buffer use efficiency is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a selective reception method in which a receiving side determines by itself whether or not to receive transmitted data based on the contents of the transmitted data.

[Prior art]

In the conventional selective reception method, information indicating whether or not to receive data C is stored in a storage device within the transmission control device according to the type of data, and after receiving the data, it is determined whether the data is necessary or unnecessary. The method of determining this using a program in the processing device was unsuccessful. ) This conventional method has the following four drawbacks. First, the load on the processing device required to determine whether data is necessary or unnecessary is large, leading to a decrease in the performance of the entire processing device.

Second, it takes time to determine whether data is necessary or unnecessary. Thirdly,
As a result, unnecessary data must also be received and buffered, which reduces buffer usage efficiency. Fourthly, in conjunction with the first and second drawbacks, the reception capability is limited by internal processing such as data necessity/unnecessity determination processing in the transmission control device. That is, the upper limit of the data transmission rate is determined by the selected reception processing time, and if the data transmission rate is increased beyond the upper limit, the storage capacity for buffering the received data must be increased.

[Purpose of the invention]

The purpose of the present invention is to improve the above-mentioned conventional drawbacks, realize selective reception in a time proportional to the data transmission speed, reduce the load on the transmitting side #device, and completely improve the buffer usage efficiency (selective reception method). il- to provide.

[Summary of the invention]

In order to achieve the above object, the present invention provides a transmission control device that performs all transmission control in which the receiving side selects data according to the contents of the received data, in which a storage device using a gold film as an address is provided with a bit string representing the contents of the received data. , stores in the storage device information @i that determines whether reception is necessary according to the type of the bit string, and when the entire bit string representing the content of the received data is received, inputs the address of the entire bit string to the storage device and stores the entire contents. All features include a means for determining whether reception of the received data is necessary or not by reading the data.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is an overall configuration diagram of a transmission control device to which an embodiment of the present invention is added. 1 is a clock recovery circuit that extracts all timing signals from the received data signal; 2 is a transmitter/receiver including a serial-to-parallel converter for the received data; and a parallel-serial converter for the transmitted data; 3 is a storage device 4 for storing the transmitter-receiver 2 and the transmitted and received data. DMAC (DMAC) for high-speed data transfer between
i rectMemory A, access Cont
5 is a processing unit (hereinafter referred to as MPU), 6 is an interface circuit for connecting the transmission control device to a computer or a terminal, and 7 is an address bus AB and a data bus Df3fc.

MP [Controls the period of J5 and DMAC5) (
A decoder selects a circuit to be connected to each of the control circuits 8 to 11. Reference numerals 12 and 13 are transmission lines connecting to other transmission control devices, and when viewed from the present transmission one-page control device, 12 is a reception signal line, and 13 is a transmission signal line. In addition, RI is the serial reception data, ttC is the clock of the reception data, FD is a flag detection signal output when the transceiver 2 detects a flag described later in the reception data ftD, and ELD8FL is the flag detection signal output when the transceiver 2 receives the data. , a signal indicating that the data exists in the reception buffer in the transceiver 2, and DSRQ are request signals for the transceiver 2 to take in the received data to the DMAC 5. AB is connected to the address bus, Ao to A15
represents 16 signals. Further, CB represents a control signal such as a timing clock such as MP (J5). DB is a data bus and represents eight signals DO to D7.

Finally, 100 is a selection receiving circuit according to the present invention. Note that in the case of the conventional method, RD8ft is directly connected to fLD8fLQ. The present invention relates to a selective reception method, and since data reception after determining that data reception is necessary and control regarding superstitions are the same as in the conventional method, a description of the operation will be omitted. Furthermore, since conventional transceivers require idle reading when not receiving data, idle reading is performed according to the conventional method.

FIG. 2 is an example of a transmission data format that can be included in this embodiment. This transmission data format is l5O
HDLC (High 1e) recommended by the International Organization for Standardization (International Organization for Standardization)
vel 1) ata, [, ink (:ontrol
) Comply with the procedure. 201 is a flag field representing the beginning of f-event; 202 is a field for a code (hereinafter referred to as function code) representing data content; 203
is a data field, and 204 is a flag field indicating the end of data.

Other fields are required due to ISO recommendations and differences in implementation methods, but they are not directly related to the present invention.
Only fields necessary for further development are shown. Note that the hardware configuration and operation, such as the bit configuration of the flag and the state when there is no data on the transmission path (idle state), are based on ISO recommendations.

FIG. 3 shows the selective receiving circuit 1 according to the present invention shown in FIG.
00 is a detailed configuration diagram. In FIG. 3, the signals input and output to the selective receiving circuit 100 are the same as those shown in FIG. 1, but the following two signals will be explained below.

DO is one signal in the data bus DB according to 2 in FIG. Further, R/W is one of the control signals CB in FIG. 1, and when the signal is high level, it represents reading, and when it is LOW level, it represents writing.

101 and 102 are Noribu frog circuits (hereinafter referred to as FF circuits), 103 and 104 are counters, and 105 is a decoder.
A15) 'i decode.

106 is a 7 foot register, 107 is a bus switch, 10
8 is a storage device, 109 is a bus switch, and 110 is a latch circuit. Also 111-118 output, N0 circuit, 11
9 to 121 are NOT circuits, and 122 is an OR circuit. Note that the signal lines in the figure are shaded and a numerical value is written (for example, a ramie) to indicate that there are signal lines corresponding to the numerical value.

The operation of the selective receiving circuit 100 in the second configuration will be divided into three types and will be sequentially explained.

(1) Operation of writing essential/unnecessary information of received data into the storage device 108.

) Operation to determine whether received data is necessary or unnecessary.

(3) Operations other than (1) and (2) above.

(1) The necessary and unnecessary data of the received data are stored in the storage device 10.
Explanation of the operation of writing to 8.

The only circuits involved in this operation are the decoder 105, bus switch 107, storage device 108, and bus switch 109. The storage device 108 has a storage capacity of 1 bit x 128 th
It has a storage capacity of 1 bit for each address selected by an 8-bit address signal. When the memory device selection signal C8 is input, the memory device 8 reads or writes the bit at the address in accordance with the 8-bit address signal. Selection of read and write operations depends on the level of the R/W signal.

Now, the address for accessing the storage device 108 from MPU 5 is ¥E000 to ¥EOFF in hexadecimal representation.
(binary display) (111000000000000
0 to 1110000011111111). Therefore, the decoder 105 is a decoder having an output when the upper eight bits of the address bus AB (AI5 to A8,1) are ¥EO.

The operation in which the MPU 5 stores the received information 1 (or O if the receiver 1d is not required) at address O in the storage device 108 is as follows. The MPU 5 outputs 1 to Do in the data bus DB, and outputs ¥E000 to the address bus AB. Also, set the R/W signal to LOW level. Address bus A
The upper 8 bits on B are decoded by the decoder 105 as described above, and the decoded output is input to the bus switch 107. The bus switch 107 is an address bus AB.
This circuit selects and outputs either the lower 8 bits of the signal or the 8-bit output of the shift register 106, and is switched by the output of the decoder 105. Decoder 1
If there is an output of 05, the bus switch 107 selects the lower 8 bits of the address bus AB, and the decoder 105
If there is no output, the output of the shift register 106 is selected as the output of the bus switch 107.

The output of the decode 105 is inputted to the selection signal C8 of the storage device 108 via the OR circuit 122. At this time,
The storage device 108 receives the selection signal C8 signal and inputs l(
/W times signal L (1' level, so the address indicated by the 8-bit address signal (in this case, address 0) is
Write the data on the data line. In this case, write ■.

The presence of 1 on the data line is due to the following operation. The output of the decoder 105 is also input to a bus switch 109, which selects either DO in the data bus DB or the signal line to the latch circuit 110. When there is an output from the decoder 105, DCI is selected.

Therefore, since the MPU outputs 1 to Do, 1 exists on the data line of the storage device 108.

As described above, the MPU 5 sequentially writes necessary/unnecessary information of received data into the storage device 108. Note that the storage device 108
The address (8 bits) corresponds to the contents of the function code field of the transmission data format shown in FIG.

(2) Explanation of the operation for determining whether received data is necessary or unnecessary.

The received data has the format shown in FIG. This operation will be explained using the timing chart shown in FIG. When the transceiver 2 of FIG. 1 detects a flag from the transmission data format shown in FIG. 2, it outputs a signal FD. The flag is ¥7E in hexadecimal. The signal FD causes the OFF' circuit 101. in FIG. i02'e are set and reset, respectively, and outputs Q and Qe are obtained. Further F'l
) are input to the clear terminal C of the counter 103 and '/shift register 106 to clear each of them. Therefore, upon input of the FD multiplied signal (the rising edge of the F'D signal in FIG. 4), the received clock signal C is input to the counter 104 and the AND circuit 115 to 118 via the ANI circuit 111.

At this time, the reason why the NOT circuit 120 has an output will be described later), and the fi and ND circuits 114 and 118 have an output if the other input is present. Therefore, the reception clock RC is AND
It is also input to the counter 103 via the circuit 118. The counter 103 outputs Q1 every time the count value is an odd value, and outputs Q4t- every time the count value is a multiple of 8.
obtain. Through the operation described later, the count value of the counter 103 reaches 9. Therefore, the AND circuit 116 obtains an output when the count value of the counter 103 is 9. Therefore,
The output of the NOT circuit 121 is present when the count value of the counter 103 is other than 9, and at that time, RC, which is the output of the AND circuit 111, is input to the clock terminal CLKK of the shift register 106 via the ANf) circuits 115 and 114. Ru. The shift register 106 is conveniently used as a serial-to-parallel converter that takes the received data RD as an input, shifts this input by 7 bits every clock, and obtains 8-bit parallel data as an output.As explained earlier, the AND circuit 116 Ha, Kara/
When the count value of 103 is 9, it has an output and N0Tl
Since the AND circuit 115 is closed via the path 121, the /store register 106 will be 7 notes eight times. When the count value of this counter 103 is 9, the ANI) circuit 11
The output of 6 is the OR circuit 122, the R, /W of the storage device 108
terminal, is input to the latch input of the latch circuit 110, and FFIjX! Reset J path 101. As a result, the AND circuit 111 is closed, and thereafter RC is no longer supplied to each section. Bus switches 107 and 10 at this time
In state 9, there is no output from the decoder 105, so the bus switch 107U selects the output from the shift register 106,
Bus switch 109 selects the signal line to latch circuit 110 instead of signal line DO. Therefore, the contents of the shift register 106 are inputted as an address signal to the storage device 108 via the bus switch 107. Also,
ANf) The output of the circuit 116 is inputted to the circuit selection signal C8 of the storage device 108 via the OR circuit 122, and is also inputted as the RAW signal of the storage device 1080. now,
Since the R/W signal is at high level, data is read from the bit position in the memory device +t108 according to the contents of the address signal, and the data is transferred to the bus switch 109.
The latch circuit 110VCt is connected through the latch circuit 110VCt. Now, when receiving data is required, if 1 is stored in the storage device, the output of the latch circuit 110 is 1, and the AN
Open the D circuit and then the signals Ft, D8RtRDSRQ
Output as . On the other hand, if the output of the latch circuit 110 is 0, the AND circuit 117 is closed, the signal RDSB does not pass, and the signals RDSR and Q remain at 0.

To summarize the above, Figure 2? -2 transmission format and according to the contents of the 7°C machine nth code field 202,
Selective reception that determines whether to accept the signals R and DSB can be realized.

Next, N0Tn path 1, whose explanation has been deferred due to the above operation.
The reason why there are usually 20 outputs will be explained. As a premise, we will explain the bit string according to the HDLC procedure described above. As mentioned above, the bit string of the flag indicating the beginning and end of data is 01111110, and 1 is 6.
Bit lasts a long time. Also, when data is not on the transmission path,
Following the flag indicating the end of data, 01111・
As shown in the following, the bit string starts with O1 and then 1, continuing until just before the flag of the next data. Continuing from the above, in data other than flags, a bit string with six or more consecutive 1 bits is not allowed because it is necessary to determine an idle state with no flag child data. Therefore, when there are five or more consecutive 1's in the actual data, the transmitter/receiver inserts a 0 into the 6th bit on the transmitting side and removes the 0 on the receiving side. This is a conventional method and is realized by.

In the present invention, since the selective reception method is realized outside the transmitter/receiver, a circuit for realizing the above operation is not required. Hereinafter, the operation of the bit string determination section centered on the counter 104 will be explained, and the output state of the NOT circuit 120 will be clarified.

The counter 104 counts the number of 1's in the received data RD using the output of the AND circuit 111 as a clock. Further, the counter 104 is cleared by 0 in the received data RD. Therefore, counter 104 counts the number of consecutive ones. The output Q1 of the counter 104 is output when the count value is an odd value, and the output Q2 is output when the count value is an even value.
The output Q3 is obtained when the count value is a multiple of 4. Therefore, when the J runt direct of 104 is a multiple of 7 (the count value is an odd value of Ql,
The AND circuit 113 outputs the output when it reaches an even value of 2 and then a multiple of 4 of Q3 (for example, if Q3 is 4, the count value at that point is 7). When the value is a multiple of 5 (AND circuit 11
As in case 2, for example, if Q3 is 4, the count value at that time is 5), and outputs are obtained respectively. The operation based on the output of the Af'JI) circuit 112 will be explained in the following (3).

The output of the AND circuit 113 is output when there is a 5-bit long series of 1's in the received data RD, and therefore, in other cases, the output of the NOT circuit 120 is in a valid state. On the other hand, if 1 continues for a length of 5 bits, NOT circuit 1
There is no output of 20, the A and ND circuits 114 and 118 are closed, and the 6th bit 0 is not input to the shift register 106. This 6th bit of 0 clears the counter 104 if it is in the middle of data.

(3) Explanation of the operation in cases other than (1) and (2) above.

As an operation other than the above (1) and (2), a case will be described in which a flag indicating the last amount of data is detected and the device then shifts to an idle state. When all flags indicating the end of data are detected, the same operation as in (2) is performed. However, in the idle state, all 1's are at the top and 1's are consecutive, so when the counter 104 counts the 7th pin of consecutive 1's after the flag is detected, the output of the AND circuit 112 is obtained. On the other hand, when there are 5 consecutive 1 bits, AND
Since the circuit 113 is outputting, the count value of the counter 103 is 6. Therefore, the υFF circuit 102 is set by the output of the AND circuit 112, and the AND circuit 11
1 closes, and then the input of the reception clock C stops. Since the count value of the counter 103 is 6, the AND circuit 116 does not operate, and the operations of other circuits also stop. It operates again when there is the next large FD input (a flag detection signal indicating the beginning of the next data).

It goes without saying that the operations (1), <2), and (3) described above are performed in proportion to the data transmission speed. This is because, as described above, selective reception can be achieved with a simple circuit configuration.

〔Effect of the invention〕

As explained above, according to the present invention, selective reception can be realized in a time proportional to the data transmission speed, the load on the transmission control device can be reduced, and buffer usage efficiency can be improved.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of a transmission control device to which all embodiments of the present invention are applied, FIG. 2 is a transmission data format, FIG. 3 is a detailed S configuration diagram of a selective reception circuit in an embodiment of the present invention, and FIG. The figure is a timing chart of the main signals in FIG.

Claims (1)

[Claims] (2) In a transmission control device that performs transmission control in which the receiving side selects data according to the content of received data, there is a storage device whose address is a pit string representing the content of the received data, and a reception request for each content of the received data. The type of the pit string indicating information for determining whether or not to be accepted is stored in the storage device, and when a pit string representing the contents of the received data is received, the pit string is inputted as an address into the storage device and the contents of the address are stored. and a means for determining whether reception of the received data is necessary by reading the fc% characteristic.