JPH0366246A - Data monitor - Google Patents

Abstract

PURPOSE:To monitor a data of a comparatively long frame by using an AND signal of a data read from a random access memory. to output a detection signal of the frame coincident with a reference data of each field. CONSTITUTION:When data D0-D7 of an address part A corresponding to the head of a reception frame from the circuit are received, a decoder 21 decodes a signal from a counter 24 and a data ('03') of the address part A is written in a register 271. Line data of registers 271-278 are inputted to address terminals of RAMs 261-268 and read by using an output data '03' of the register 271 as an address and an output data D00 goes to logical 1. Thus, an address part A of '03', a control field C of one frame command and a general format identifier GFI of '02' or the like are selected from a multiplexed frame on the line in this way.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a function for rapidly selecting a specified frame from multiplexed frames on a communication line, hereinafter referred to as a selective trace function. ).

2. Description of the Related Art In general, in data communication, multiplexed frames on a communication line are monitored frame by frame by selecting a specific address or channel (logical channel for packets) (selective trace function).

This function is essential for analyzing the difference between the data on the multiplexed line and the data on the line captured at the terminal side. can be received by the terminal.

Conventional data monitor devices that realize this selective trace function use an extremely high-speed central processing unit (CPU) or are constructed solely of multiple combinational circuits.

Problems to be Solved by the Invention However, data monitoring devices using the above-mentioned high-speed CPUs have the problem of being expensive, and data monitoring devices using complex combinational circuits require a lot of processing time. and especially LAPD (Link Accesses
s Procedure on the D-chan
When monitoring data in which the length of the frame to be selected is 40 bytes or more, such as in the case of ``nel'', the circuit configuration becomes even more complicated.

In view of the above conventional problems, the present invention has a simple circuit configuration,
It is an object of the present invention to provide a data monitoring device that can monitor relatively long frame data.

Means for Solving the Problems In order to achieve the above object, the present invention provides a plurality of random accesses for storing data "1" in advance in an area of an address corresponding to a reference data value of each field of a frame on a line. The standard of each field is determined by a memory, multiple registers that store the data of each field of the frame on the line and output to the address terminal of the random access memory, and an AND signal of the data read from the random access memory. It is equipped with an AND circuit that outputs a detection signal of a frame that matches the data.

Operation The present invention has the above configuration, and includes a random access memory,
The circuit configuration is simple because it can be configured with shift registers and AND circuits, and by increasing the number of random access memories and shift registers according to the frame length, data in relatively long frames can be processed easily. can be monitored.

EXAMPLES Hereinafter, the present invention will be described in detail with reference to the drawings. 1 is a block diagram showing an embodiment of a data monitor device according to the present invention, FIG. 2 is a circuit diagram showing a detailed configuration of the selective trace circuit shown in FIG. 1, and FIG. 3 is a circuit diagram showing the detailed configuration of the selective trace circuit shown in FIG. FIG. 4 is an explanatory diagram showing the frame structure of received data in
FIG. 4 is an explanatory diagram showing the byte structure of the received data in FIG. 3;

In FIG. 1, 11 is a line through which the components of the HDLC frame structure are transmitted, and one frame consists of an open flag 31 and an end flag 32 placed at the beginning and end, respectively, as shown in FIG. , an address field A for specifying a station address, etc., a control field C,
The information frame is composed of field I and so on, and each field is composed of 8 bits.

The first information field I consists of a 4-bit general format identifier GFI and a 4-bit logical channel number LCN.

Returning to FIG. 1, 12 is a communication control LSI for receiving data on the line 11, and 13 is a communication control LSI 112.
A central processing unit (C
As will be described later, the selective trace circuit 14 compares the reference initialization data with the received data, and if they match, outputs a match signal to the CPU 3, and also outputs a match signal to the CPU 3, and 15 displays data etc. under the control of the CPU 13.

In FIG. 2, 21 is an 8-bit register (REGI~8) 271.2, respectively, depending on the value of the counter 24.
It is a decoder that outputs addresses to 72 to 278, and registers 271 to 278 are n
It is connected to 14 columns and stores the data of each field of the data received from line 11.

22 stores the address Ao=At according to the reference initialization data value under the control of the CPU 13 in 8-bit random access memories (RAM1-8) 26', , 26
2 to 268; 23 is the gate for feeding to the CPU 13;
Data “1” is transferred to RAM 26+, 262
This is a gate that outputs data to the data input terminal DI□ of ~268.

The data output terminals of registers 271 to 278 are each
Connected to address terminals of RAM 26, ~26B,
RAM 261-268 data output terminal DOO""
'DO7 is connected to the input terminal of the AND gate 25. The output signal of the AND gate 25 is output to the CPUI 3 as a coincidence signal indicating that a predetermined frame of the multiplexed frames on the line 11 has been detected.

Next, the operation of the above embodiment will be explained.

As shown in FIG. 4, the address field A is "03", the control field C is ■ frame (even number designation), the general format identifier GFI is "02", the logical channel group number LCGN is "05", and the logical channel Number LCN
The operation when detecting a frame where is "06" will be explained.

First, transfer the above initialization data to RAM26□, 26°~2
The operation when writing to 68 will be explained.

The gates 22 and 23 are enabled under the control of the CPU 1'lt, and the addresses "03", "even address", "25", "06", and "all four addresses" corresponding to the initialization data value are gated. RAM261 26 through 22
□ to 268 respectively, and the data “1”
” is RAM 26 + , 262 through gate 23
~268 data input terminals D+o-D17.

Next, in response to a write command from the CPU 13, the RAM 26
Data "1" is written to address "03" of +, and data rOJ is written to other addresses.

Further, since the control field C specifies one frame and is an even number, data "1" is written to the even number address of the RAM 262, and data "o" is written to the odd number address.

Similarly, address “25” of RAM 26 s and RAM 2
Data “1j” is written to address “06” of 64, and RA
Data "O" is written to other addresses of M268.264. Data "1" is written to all addresses of RAMs 265-268.

When writing of the initialization data to the RAMs 26 r to 268 is completed, the gates 22 and 23 are disabled under the control of the CPtJ13, and the counter 24 is reset.

When data D0 to D7 of the address part A corresponding to the beginning of the received frame from the line 11 is input, the decoder 21 decodes the signal from the counter 24, and therefore the data of the address part A ("03") is transferred to the register 27. ．． will be written to. Note that the data bus of the register 271 at this time is in an input enable state.

Next, the counter 24 counts up the write pulse WT by one to manually enable the data bus of the register 272, so that the received data (“02”) corresponding to the control field C is written to the register 272.

Similarly, received data (r25J) corresponding to the general format identifier GFI and logical channel group number is written to register 278, and received data (“06”) corresponding to the logical channel number is written to register 274.

The line data in registers 271-278 are then input to address terminals of RAMs 261-268, respectively.

Here, since the address "03" is set in the RAM 26+, this data is read out using the output data "03" of the register 27□ as the address, and becomes the output data D.

0 becomes data "1".

Similarly, the data in RAMs 262 to 2611 are read out using the output data of registers 272 to 278 as addresses, and the output data D2 to DB are all data "
1”, the output data of AND key 1/25 becomes “1”.
”.

That is, from the frame multiplexed on the line 11, the address part A is "03", the control field C is an I frame indication, and the general format identifier GFI is "0".
2”, logical channel group number LCGN is “05”,
The frame with the logical channel number J,, -1-CN of "06" can be selected, and therefore the RAM 26. ~2
An arbitrary frame can be selected by presetting data "1" in an arbitrary address area on the 6th.

In the above embodiment, the 8-bit address RAM
Since 261 patterns are used, 256 patterns can be selected.

In addition, when selecting a longer frame, R0 AM 261-268, register 27. It is possible by extending ~278, and the search time is
Access time and gate 22 for AM261-268
．． Since there is only a delay time caused by 23, high-speed processing is possible.

Further, according to the above embodiment, selective tracing of attributes such as data comparison, bit mask, and don't care can be processed at low cost and at high speed.

DETAILED DESCRIPTION OF THE INVENTION As described above, the present invention includes a plurality of random access memories for storing data "1" in advance in an area of an address corresponding to a reference data value of each field of a frame; A detection signal for a frame that matches the reference data of each field is output by using multiple registers that each store data and outputting it to the address terminal of the random access memory, and an AND signal of the data read from the random access memory. Equipped with an AND circuit, the circuit configuration is simple, and by increasing the number of random access memories and shift registers according to the length of the frame, data in relatively long frames can be monitored. .

[Brief explanation of drawings]

1 is a block diagram showing an embodiment of a data monitor device according to the present invention, FIG. 2 is a circuit diagram showing a detailed configuration of the selective trace circuit shown in FIG. 1, and FIG. 3 is a circuit diagram showing the detailed configuration of the selective trace circuit shown in FIG. Explanatory diagram showing the frame structure of received data in 4th
The figure is an explanatory diagram showing the byte structure of the received data in FIG. 3. 11...Line, 12...Communication control LSI, 13...
- Central processing unit (CPU), 14... selective trace circuit, 21... decoder, 22.23... gate, 24... counter, 25... AND gate,
261 to 268...Random access memory (RAM)
), 271-278...Register (REG).

Claims (2)

[Claims] (1) Multiple random access memories for storing data "1" in advance in areas of addresses corresponding to the reference data values of each field of frames on the line, and storing data of each field of frames on the line, respectively. a plurality of registers that output to address terminals of the random access memory; and a logic that outputs a detection signal of a frame that matches the reference data of each field based on an AND signal of data read from the random access memory. A data monitor device having a product circuit. (2) The data monitor device according to claim (1), wherein the register is connected in parallel to the line.