CA1238421A - Microprocessor interface device for use in a telecommunications system - Google Patents

Abstract

ABSTRACT
MICROPROCESSOR INTERFACE DEVICE FOR USE IN A
TELECOMMUNICATIONS SYSTEM.
The microprocessor interface device is for use in a telecommunications system including a microprocessor. The device includes a first interfacing means which receives signals from, and despatches signals to, the telecommunications system. A second interfacing means receives signals from, and despatches signals to, the microprocessor. A memory is provided, together with arbitration means arranged to control the first and second interfacing means so that only one interfacing means at a time has access to the memory. Decoding means is adapted to respond to address signals presented to the second interfacing means by the microprocessor, to generate signals enabling areas of the telecommunications system to be accessed.

Description

I

TITLE: MICROPROCESSOR INTERFACE DEVICE FOR
USE It A TELECOMMUNICATIONS SYSTEM
The invention relates to a microprocessor interface device for use in a telecommunications system. The device provides a 32 byte two-port processor interface which acts as a two-port buffer.
An aim of the present invention it to provide a microprocessor interface device for use in a telecommunications system.
According to the present invention there is provided a microprocessor interface device, for use in a telecommunications system including a microprocessor, wherein the device includes a firs-t interfacing means for receiving signals from and dispatching signals to, the telecommunications system, a second interfacing means for receiving signals from, and dispatching signals to the microprocessor, a memory, arbitration means arranged to control the first and second interfacing means so that only one interfacing means at a time has access to the memory, and, decoding means adapted to be responsive to address signals presented to the second interfacing means by the microprocessor, and to generate signals enabling areas of the telecommunications system to be accessed.
on aspect of -the present invention is to provide a microprocessor interface device wherein the first interfacing means includes a buffer for receiving a clock signal which is passed to a delay circuit arranged to delay the clock signal and generate under control of the arbitration means, an acknowledgement signal which is used to indicate that a system bus has been granted access to the memory.
A further aspect of the present invention is to provide a microprocessor interface device wherein the second interfacing means includes circuitry for generating a signal indicating to the microprocessor that access to the memory has been granted in response to a memory request signal generated by the microprocessor, and circuitry for generating a signal to enable the memory area so that the memory can be accessed.
An embodiment of the present invention will now be described with reference to the accompanying drawings wherein, Figure 1 shows a block diagram of part of a telecommunications system, Figure 2 shows a memory map of two-port decoder outputs, Figure 3 shows a block diagram of a two-port gate array, Figure 4 shows a block diagram of a system bus interlace, Figure 5 shows the signals used by and generated by an arbitration circuit, Figure 6 shows a random access memory and associated memory decode, Figure 7 shows decode circuitry, Figure 8 shows waveforms for a system interface read I

Seiko, Figure 9 shows waveforms for a system interface write cycle, Figure 10 shows waveforms for a host microprocessor, Figure 11 shows a decode output timing waveforms, and, Figure 12 shows control timing waveforms.
Referring to Figure 1, the system block diagram shows a microprocessor A controlling a 32 byte two-port processor interface B, which is the subject of the present invention, a universal program bus selector C, a cyclically per mutable code generator detector D; and a subscriber line interface modem E.
The microprocessor A communicates with the units B-E
by way of the addrsss/data bus ADDR/DATA. The microprocessor A generates control signal INTO for unit D, signals ROD, WRY for units B-E, signal ALE for units B, D, E and unit AL, and request signal BAR for unit B. Unit B acts as a two-port buffer with arbitration between the self system bus and the microprocessor A. Unit B receives shelf control bus signals SOB and generates a transfer acknowledgement signal JACK and signal RESET. A low order shelf address bus LO, and a high order shelf address bus HO is provided, the latter being connected to a module enable decoder MUD, which is connected to a module position address bus MY. Mode A and B inputs are provided to selectively control the mode of operation of the unit. A

data bus DUB, feeds into and out of the unit B, unit a generates a decode signal Of for units C, D and E and a request granted signal sag for the microprocessor A.
A local decode circuit LOO generates a local decode signal Of for the unit.
The universal prograr~nable bus selector C provides a common interface between six single channel digital traffic terminations operating at 32K bits per second.
It receives TAM signals at lo bit per second and transmits TAM signals out at lo bit per second. The unit has an address latch input to which the address latch AL
is connected.
The units A, and C belong to a Coleman area and the units D and E belong to a digital voice terminal interface area.
The cyclic per mutable code generator detector D
detects and generates cyclically per mutable codewords on any of six independent channels and is controlled by a standard microprocessor interface. Eleven registers provide command and status information for full control.
A codeword is detected if incoming serial data contains any eight bit word repeated six times consecutively.
Generation of a codeword is by continuous serial transmission of a data byte loaded by the control interface. The unit D receives traffic from units C and E and transmits -traffic to units C and E.
The subscriber line interface modem E interfaces between the multiplexed traffic highways from unit D and six line interface circuits LIT forming the channel rate 4-wire digital voice terminal loops to the subscribers.
Each of the units C, D and E receive a framing and a lMHz clock signal from a clock buffer CUB.
Each line interface circuit comprises trapezoidal line drivers LO, line receivers LO, and a current limiter CAL. The subscriber line inputs are shown as IT and the outputs OP.
The microprocessor interface device will now be described in detail.
The device primarily acts as a 32 x 8 two-port buffer, with arbitration between the shelf system bus and the processor. Messages are passed to and from the device for control and signaling reporting. The device connects directly to the system bus with the addition of a comparator to provide the 'module enabled' signal transfer acknowledge JACK Signals axe generated as appropriate on chip.
The device takes in the multiplexed address data bus of the host microprocessor for access to the two-port memory and for the address decoding section. In the simple host microprocessor mode the BAR/BAG signals are used to request access by the microprocessor and 'permission granted' in reply.
In the case where the host processor is capable of being held in wait-states then the DOW signal is used to control host access, the use of BAR/BAG being unnecessary.

~23~

The device provides two modes of address decoding for thy microprocessor. This is used to eliminate extra decoders when driving hardware registers and/or other addressable devices.
The selection of mode is hand-wired by use of the input 'mode A, mode B' in accordance with the Truth Table below.
A B Mode 0 0 Wait state-able host processor l 0 DECODE TYPE l) Simple host processor l 1 DECODE TYPE 2) External Memory Eighteen general purpose connections act as address, data and control to an external jam.
.
The connections act as chip select outputs for external devices.
Decode Type 2 Decoding from addresses is the same as Type 1. The connections act as chip selects for one external device The other connections provide output enable and latch signal for read and write ports respectively.
Decode 1 gives use of SHEA and Roy 0-3, and decode I 2 gives uses of SHEA and Rug 0-7 as shown in Figure 2.
The typewrote memory not shown, is enabled separately by host interface chip select signal US. The US signal may be derived from independent decoding allowing the I
- a two-port to be placed anywhere in the host memory space.
The device may be split into six functional areas.
a. System Bus Interface, SKI.
b. Host Bus Interface, HI.
c. Arbitration circuits, ART.
d. RAM and RAM decode, RAM, RAMDC.
e. Card Control Logic, CAL.
I Decode circuit, DEC.
These areas are interconnected as shown in Figure 3, to which reference should be made in conjunction with the following Figures System Bus Interface, SKI.
This device area provides buffering and acknowledge signal generation for the system interface. The area has five external control signals, two of which go directly to the arbitration area. The byte wide address and data buses of the system bus are also buffered onto the chip to be selected as appropriate to the memory area.
The control signals are shown in Figure 4. A
buffer Burl receives the write, read and clock signals AWRY ART and CCLK respectively. The write and read signals are passed to control a memory by way of lines MUM and delay satiny circuitry DUG. The circuitry is enabled by signal En from the arbitration circuit ART.
The delay generator DELL generates a transfer acknowledgement signal JACK for presentation to the system bus interface I/F by way of a buffer BFR2.
A module enable signal MEN is passed directly to I

g the arbitration circuit ART.
HOST BUS INTERFACE, HI
In this mode memory access is granted by the signal denoted by signal BAG representing bus access granted as shown in Figure 10.
The BAR signal indicates that the memory is required and is passed to the arbitration circuit ART.
The signal BAG occurs as soon as the memory access is granted. This signal is polled by the software in the microprocessor before accessing the memory.
The chip select signal US is used to signal the memory access.
Arbitration Circuits, ART. Figure 5.
The arbitration area of the device ensures that only one of the two bus interfaces has access to the RAM area at any time. The circuit locks-out a port when the owner is using the RAM.
The circuit has two signals between itself and each of the bus interface areas, one input and one output.
The input signals acts as a request for access to the RAM. The output acts as a grant signal.
If one of the interfaces raises a request whilst the memory is busy, the arbitration circuit does not give a grant signal. The devices connected to each interface must inspect -the grant line after requesting access, and only access the memory if a grant is yiven.The simple host microprocessor does this with signals BAR and BAG.

RAM and RUM Decode Areas, JAM, RAMDC. Figure 6.
The internal memory is organized as a 32 by 8 bit array. The memory is enabled when the mode 'A' input is '1' otherwise an external memory chip is used.
The RAM area is enabled as soon as a memory access is sensed. This is signified for the system and host interfaces by the MEN signal active or the US signal active respectively.
Card Control Logic, CAL.
This area of the device performs the miscellaneous grating required for card reset and online functions as required. The logic provide an output 'reset' which responds to either a low on the power on reset PRO input or the coincidence of WORRY, MEN and software Reset Syria The PRO input is driven by a capacitor-resistor network.
The 'module off line' signal OPT is grated into the arbitration logic to allow the system bus interface outputs to be forced to a instate condition.
Decode Circuit, DEC. Figure 7.
The Decode area of the devices responds to the latched address of the host interface HI. The decode circuit takes the high nibble of the address Aye and decodes to sixteen outputs. The sixteen outputs are then either presented directly to the outputs or further decoded with the address Aye and grated with -the interface 'write and read' controls (BAR, BUD). The former method provides chip select outputs for 'memory like' sixteen byte long peripherals, such as the , universal program bus selector.
The latter method, grating with write and read, allows direct connection of single byte registers, such as an output latch and an input buffer with output enable. Hence, the interface device decode outputs are taken directly to the latch and output enable connections of the peripheral devices respectively.
A decode enable signal enables the decoder outputs when it is 'zero'. The signal may be driven by external high-order decoding in order to place the decoder of the interface device more specifically in the host memory space.
INTERFACES.
Functional Pin Dose_ potions.
lo Buy A Interface.
Address Inputs Active low.
These signals provide the byte addresses from the two port RAM. They connect directly to the system bus address lines.
Data Inputs/Outputs AUDI.
These signals provide the parallel bidirectional connection to the shelf bus. Data is driven from the outputs when a shell read cycle occurs.
rite Input AWRY Read Input ART.
Active low.
The signals indicate to the device when a write and read cycle is occurring on the system bus.

Module Enabled Input MEN.
_ Active low.
This signal indicates to the device that a system bus access is going to occur. The input is derived from S an external decode of the higher system bus address bits.
Constant Clock Input CCLK.
Active low.
This signal provides the acknowledge of circuitry timing reference and is a buffered version of the system bus signal CCLK.
Transfer Acknowledge Output JACK.
_ Active low. Tristate.
This signal is generated after the system bus has been granted access to the memory area. The signal is delayed by seven periods of signal CCLK to allow for the memory access time. The signal drives the system bus JACK signal directly.
us B Interface.
This interface is similar to bus A in function.
Address/Data Bus B_ directional BAD 0-7.
Active high. Txistate.
This bus connects the device to the multiplexed address and data bus of the microprocessor. The addresses are latched within the device in response to signal Alto Address Latch Enable Input ALE.
Active high.

On the negative edge of this signal the address of the current cycle is stored.

Write Input BAR and Read Input BUD.
Active low.
These signals indicate to the device when a write or read cycle is occurring from the microprocessor.
Chip Select.
Active low.
This signal, when active, enables the two-port memory section of the two-port processor. The input it asserted by the microprocessor decode logic in response to an address.
Bus Access Request BAR.
Active low.
The BAR signal is used to inform the two-port section that the microprocessor wishes to gain access to the two-port memory (modes 01, 10 and 11 only.
Bus Access Grant BAG.
This signal becomes active when the two-port arbitration logic allows access to the memory. The signal is polled by the microprocessor -to determine when to access the bus. This signal is also used as direction control for external memory address.
External Memory Interlace.
This interface provides address, data, write and read controls. These signals may be used to extend the internal 32 x 8 memory upwards.

The interface shares the same group ox outputs as I

the decoder outputs. The state of MODE inputs determines which role the outputs adopt.

External Memory Address ETA 0-7.
Active low.
These signals form the preselected low order address for the external memory.
External Memory Data END 0-7.
Active low. Tristate.
These signals form the preselected data bus for the external memory.
External Memory Read Control ERR.
Active low.
This signal drives the output enable pin of the external memory. The signal is preselected from the Read signals of the A and B ports.
External Memory Write Control EWE.
Active low.
This signal drives the write input of the external memory and is preselected from the write signals of the A and B ports.
Decoder Outputs.
These signals replace the external]. memory interface when MODE A = lo The decoder outputs themselves split into two types depending on the state of the MODE B
signal.
Card Control and Mode Inputs.

Mode A and B Inputs MA, MY.
Active high.

ox These signals set the operational modes of the devices. The inputs have internal pulps and require only links to OX to program the device.
Module Output Disable OPT Input.
_ Active low.

This signal when low, disables Port A outputs.

Power On Reset PRO Input.
-Active loathes signal directly influences the RESET output.
The input is connected to an external capacitor to ground.
Software Reset SIR Input.
Active low.
This signal is taken from all of the system bus.
When SIR, AWRY and MEN are all active the YES output it active. The SIR input may be driven by external address decoding.
Reset RYES Output.
Active low.
This signal is used to drive the reset of the microprocessor and miscellaneous reset and clear signals.
Interface Timings.
The timings for the device interfaces are shown in Figures 8-12.
RAM minimum specification is as follows:

Write (no) Address to write active. 70 Address to write strobe edge. 380 I

(no) Data set up time to write strobe edge. 340 Data hold time from write strobe edge. 30 Address hold time from write strobe edge. 30 Write pulse width required. 165 Read Address to data out. 200 Read to data out. 400 Data Tristate after Read 40 Cyst m Interface Figures 8 and 9.
General.
Mix no Max no 1. -Required module enable/address/data 0 to command set up time.

2. Required module enable/address/data 0 to command hold time.

3. Command active to Jack driving. 0 60

4. Command active to Jack active

5. Command inactive to XacX Tristate. 0 55 20 6. Required command hold after Jack 0 active.
Write 7. Required data hold after Jack active. 70 Read 25 8. Read active to A data drive. 0 45 9. Read inactive to A data tristate.0 75 10. Address valid to valid data out. 395 11. Read active to valid data out. 345 _ 17 Host I/F Microprocessor. Figure 10.
General.
1. BAR to BAG low. 0 75 2. BAR to BAG high. 0 65 3. Required address to command set up. 140 4. Required address/data to command 70 hold time.
5. Chip select address/data to command 35 set up.
Mix no Max no

6. Required address to ALE negative edge 40 set up.

7. Required address to ALE negative edge 10 hold time.
Write

8. Required write pulse width 145 Data set up time before write positive edge.
Read.
20 9. Address to data valid. 390 10. Read to data valid. 250 11. Read to data driving. 75 12. Read to data Tristate~ 0 75 Decode Outputs. Figure 11.
25 1. Address to chisel active. - 150 2. Jew address to chisel inactive. - 120 3. Command active to fog 0/P active. - 130 4. Command inactive to fog 0/P inactive. -110 ~2~8~

5. DECODE EN to chisel active. - 140 6. DECODE EN to chisel inactive. 100 Card Control logic. Figure 12.
1. Reset output active time. 2 Depends on PRO
capacitor

Claims (6)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY OR
PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A microprocessor interface device, for use in a telecommunications system including a microprocessor, wherein the interface device includes a first interfacing means for receiving signals from, and despatching signals to, the telecommunications system, a second interfacing means for receiving signals from, and despatching signals to the microprocessor, a memory, arbitration means arranged to control the first and second interfacing means so that only one interfacing means at a time has access to the memory, and, decoding means adapted to be responsive to address signals presented to the second interfacing means by the microprocessor, and to generate signals enabling areas of the telecommunications system to be accessed.

2. A microprocessor interface device as claimed in claim 1, wherein the first interfacing means includes a buffer for recovering a clock signal which is passed to a delay circuit arranged to delay the clock signal and generate under control of the arbitration means an acknowledgement signal which is used to indicate that a system bus has been granted access to the memory.

3. A microprocessor interface device as claimed in claims 1 or 2, wherein the second interfacing means includes circuitry for generating a signal indicating to the microprocessor that access to the memory has been granted in response to a memory access request signal generated by the microprocessor, and circuitry for generating a signal to enable the memory so that the memory can be accessed.

4. A microprocessor interface device as claimed in claim 1 or 2, wherein the decoding means responds to the address signals presented to the second interfacing means and decodes output signals from part of the address to provide select signals for peripherals of the telecommunication system, or the output signals are decoded with the remaining parts of the address to allow direct connection of single byte register means.

5. A microprocessor interface device as claimed in claim 1 or 2, wherein the second interfacing means includes circuitry for generating a signal indicating to the microprocessor that access to the memory has been granted in response to a memory access request signal generated by the microprocessor, and circuitry for generating a signal to enable the memory to that the memory can be accessed, and wherein the decoding means responds to the address signals presented to the second interfacing means and decodes output signals from part of the address to provide select signals for peripherals of the telecommunication system, or the output signals are decoded with the remaining parts of the address to allow direct connection of single byte register means.

6. A telecommunications system incorporating a microprocessor interface device as claimed in claim 1 or 2.