JPS5839421B2 - super receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION An object of the present invention is to simplify the configuration for digitally displaying a received frequency in a synthesizer receiver, and particularly to reduce display errors.

First, an example of a synthesizer type double super receiver will be explained with reference to FIG.

In this example, the receiving frequency band is 1 to 30M.
Hz, which is divided into 29 bands of IMHz each,
This is a case where each band can receive any frequency of that band.

In Fig. 1, 1 is an antenna, 2 is a preselector,
As a result, a received signal of 1 to 30 MHz is extracted, and this received signal is supplied to a variable bandpass filter 4 through a high frequency amplifier 3, and a received signal of a desired band is extracted.

This received signal is then supplied to the first mixer circuit 5, and is also supplied to the first local oscillation circuit, that is, the VCO to be described later.
An oscillation signal from the (voltage controlled variable frequency oscillation circuit) 21 is supplied to the mixer circuit 5 as a first local oscillation signal.

Therefore, in the mixer circuit 5, among the signals received from the filter 4, only the signal of the desired receiving frequency is frequency-converted to a first intermediate frequency store name whose carrier frequency is, for example, 45.145 MHz, and this first intermediate frequency signal is The signal is supplied to the second mixer circuit 7 through the first intermediate frequency amplifier 6.

A second local oscillation signal having an oscillation frequency of 45.6 MHz is also supplied to the mixer circuit 7 from a second local oscillation circuit 11 using a crystal oscillator.

Therefore, in the mixer circuit 7, the first intermediate frequency signal is
The frequency is converted into a second intermediate frequency signal having a carrier frequency of 455 kHz, this second intermediate frequency signal is supplied to the detection circuit 9 through the second intermediate frequency amplifier 8, and the detected signal is taken out at the terminal 10.

And the first local oscillation is the second local oscillation circuit 11, V
It is formed by the FO (variable frequency oscillation circuit) 12 and PLL 20 as follows.

That is, in the VFOl2, an oscillation signal whose frequency changes between 3.455 and 2.455 MHz is formed in response to the dial operation, and this oscillation signal is sent to the mixer circuit 1.
At the same time, the second local oscillation signal from the second local oscillation circuit 11 is supplied to the mixer circuit 13, and from the mixer circuit 13, a beat signal whose frequency changes between 42.145 and 43.145 MHz is supplied to the mixer circuit 13. A signal is taken out, and this beat signal is supplied to a mixer circuit 22 through a bandpass filter 14, and this mixer circuit 22 is further provided with a VCO.
An oscillation signal from 21 is supplied.

In this way, a beat signal having a frequency that is the difference between the two signals supplied thereto is extracted from the mixer circuit 22.

This beat signal is then supplied to the frequency divider circuit 24 through the low-pass filter 23, where it is divided into 1/2 frequency, and this frequency-divided signal is further supplied to the variable frequency divider circuit 25, where the frequency is reduced to 1/N. Divide the frequency.

In this case, the frequency division ratio 1/N is changed between 1/4 and 1/32 (N=4 to 32) depending on the reception band.

This frequency-divided signal is then supplied to the phase comparison circuit 26, and at the same time, the fixed oscillation circuit 27 having a crystal oscillator
The kHz oscillation signal is supplied to the comparator circuit 26, the frequency-divided signal and the oscillation signal are phase-compared, and the comparison output is V.
It is supplied to CO21 as its control signal.

Therefore, in a steady state, the frequency of the frequency-divided signal from the frequency divider circuit 25 is the oscillation frequency of the oscillation circuit 27, which is 50
Since it is equal to 0k)Tz, the frequency division ratio of the frequency divider circuit 25 is 1.
For example, when /N is 1/4 (N4), the frequency dividing circuit 24
The frequency of the frequency-divided signal from the mixer circuit 22 is 2 MHz, and the frequency of the beat signal from the mixer circuit 22 is 4 MHz.

In this case, the oscillation frequency of the VCO 21 is the sum of the frequency of the beat signal from the filter 14 and the frequency of the beat signal from the mixer circuit 22, and the frequency of the beat signal from the filter 14 is the frequency of the beat signal from the FO 12. 42.145~43.145MH according to dial operation
Varies between z.

Therefore, in the case of 1/N=174, VCO21 outputs 46°14 in response to the VFOI 2 dial operation.
An oscillation signal whose oscillation frequency changes between 5 and 47.145 MHz is obtained.

On the other hand, when the frequency division ratio 1/N of the frequency dividing circuit 25 is 1/32 (N=32), the frequency of the beat signal of the mixer circuit 22 is 32 MHz, so in this case, from the VCO 21, 74.1 in response to VFOl 2 dial operation
An oscillation signal whose oscillation frequency changes between 45 and 75.145 MHz is obtained.

That is, in general, the frequency of the beat signal is N (MHz) due to the mixer circuit 22, so ■CO2,1
From 'VCO12 dial operation (42
, 145+N) to (43,145+N) (MHz).

This oscillation signal is then supplied to the first mixer circuit 5 as a first local oscillation signal, and the first intermediate frequency is 4.
5.145 MHz, the receiving frequency band is 1 to 30 MHz, and in that case, the receiving band can be switched in I MHz units by changing the frequency division ratio 1/N of the frequency dividing circuit 25. At the same time, VF
By changing the oscillation frequency of Ol2, it is possible to receive any frequency in each reception band.

However, in this case, the relationship between the reception frequency and the oscillation frequency of VFOl2 is as shown in FIG.

That is, in FIG. 2, the frequency division ratio 1/N of the frequency dividing circuit 25 is 1.
/4, which shows the relationship between the receiving frequency when receiving the 1 to 2 MHz band and the oscillation frequency of VFOl2.As shown in this figure, the higher the receiving frequency, the higher the VFO
The oscillation frequency of I2 becomes lower.

Therefore, when digitally displaying the received frequency using the oscillation signal of the VFO 12, as shown in FIG.
The oscillation signal from the FO 12 is supplied to the frequency converter 61, and the frequency is 3.455 M from the oscillation circuit 62.
A Hz oscillation signal is supplied to the converter 61 and the VFO 12
When the oscillation frequency changes between 3.455 and 2.455 MHz, a beat that changes between 0 and IMHz obtains a signal, which is supplied to the counter device 63 to digitally display the order of (kHz). This method is a common method.

However, in this case, since the oscillation circuit 62 and the converter 61 are provided, the configuration becomes complicated and the cost increases.

In addition, spurious beats occur due to the oscillation signal from the oscillation circuit 62 and the beat signal from the converter 61.

Furthermore, if there is a drift or shift in the oscillation frequency of the oscillation circuit 62, this will appear as an error in the display frequency.

In view of these points, the present invention attempts to enable reception frequencies to be displayed digitally with high accuracy without providing the oscillation circuit 62 or converter 61.

Now, in Fig. 2, when the receiving frequency and the oscillation frequency of VFO 12 are added, the sum frequency is 4.455.
It is constant at MHz.

Therefore, the oscillation frequency of VFO 12 for 4.455 MHz, the complement frequency of 3.455 to 2,455 MHz is:
1 to 2 MHz, and its complement frequency (kHz,
) corresponds to the (kHz) order of the reception frequency.

Therefore, in the present invention, as shown in FIG. 1, a down-count type counter device 30 for displaying the reception frequency is provided, and the oscillation signal of the VFO 12 is supplied as the count input, and the counter device 30 is of the down-count type. When resetting the device 30 for each count, e.g.
Reset to 55 kHz.

That is, in FIG. 1, 31 to 34 are decimal counters, which are connected in series to count down the input pulse.

Then, the oscillation signal from the VFO 12 is supplied to the gate circuit 37 as its gate power, and the oscillation signal from the oscillation circuit 27 is supplied to the frequency dividing circuit 38.

4, and this frequency-divided signal is sent to the gate circuit 37.
The gate circuit 37 takes out the oscillation signal from the VFO 12 while the signal is rising (this is 10 msec), and this gate output is sent to the counters 31 to 34. are supplied in series,
In the counters 31 to 34, 0.1, 1 of the receiving frequency
, 10, and 100 kHz are counted down, respectively.

The count contents of the counters 31 to 34 are displayed on digital display elements 51 to 54 through latch circuits 41 to 44.
The received frequencies of the order of 0.1, 1, 10, and 100 kHz are digitally displayed in the elements 51 to 54, respectively.

At this time, the frequency divided signal from the frequency dividing circuit 38 is supplied to the latch control circuit 49 to form a latch control signal,
This control signal is supplied to latch circuits 41-44.

Furthermore, 55 and 56 are digital display elements that digitally display the received frequency of the order of 1.10 MHz, which, together with the band pass filter 4 and the frequency dividing circuit 25, are switched by a band changeover switch 40 and supplied with a driving voltage. , the receiver is adapted to display the frequency in the order of MHz.

Further, 39 is a reset circuit, in which the frequency divided signal from the frequency dividing circuit 38 is supplied to the reset circuit 39 to form a reset signal, this reset signal is supplied to the counters 31 to 34, and the counters 31 to 34 are set to the gate. - Prior to counting the gate output from the gate circuit 37, the counter 31 to
34 resets are performed.

However, in this case, the contents of the counter 31 are reset to "0" by this reset signal, but the contents of the counter 32 are reset to "0".
．． 33 is configured such that its content is reset to "5", and the counter 34 is configured such that its content is reset to "4".

In such a configuration, for example, N=4 and VFO1
If the oscillation frequency of No. 2 is 2.955 MHz, the receiving frequency will be 1.5 MHz as shown in FIG.

In this case, the gate period of the gate circuit 37 is 10 m.
Since it is a second, the gate circuit 37 outputs 2.955 x 106 x 10
5029550 cycles are supplied to counters 31 to 34,
will be counted down.

However, at this time, the counters 31 to 34 are rOJ,
r5Jr5J, has been reset to l'-4J.

Therefore, the contents of the counters 31-34 change as shown in FIG.

That is, the contents of the counters 34 to 31 decrease by Ill for each input pulse, but the contents decrease from the state where it is reset to "4550" and become "o O00J".
Then, when the next input pulse is counted, the content becomes J9999J, and thereafter decreases again with each input pulse.

Therefore, the down count in the counters 34 to 31 does not become 4550-29550 nee 2500, but becomes a subtraction as shown in FIG. 4 (* is an integer of 3 or more).

At that time, the highest digit of the count result (*-1-2)
is a higher digit than the counter 34, so it overflows and the counters 34 to 31 receive the second to upper digit of the count result.
The lowest digit "5000" is obtained.

Since this content is supplied to the display elements 54 to 51, the elements 54 to 51 receive this reception frequency of 1.5 MHz.
J500. which is on the order of (kHz). OJ is displayed.

At this time, the display element 56 is turned off by the band changeover switch 40, and [1] is displayed on the display element 55.

Therefore, the receiving frequency is displayed as "1.500.OJ" by the elements 55 to 51.

The above operations are performed similarly for other bands and reception frequencies.

In this way, the received frequency can be digitally displayed. In this case, according to the present invention, the down counter device 3
0 is only required, and the oscillation circuit 62 and converter 61 are not required as in the example shown in FIG. 3, so the configuration does not become complicated and costs can be reduced.

Furthermore, since frequency conversion by the oscillation signal of the oscillation circuit 62 is not required, word differences in display due to frequency drift or deviation of the oscillation signal do not occur.

Further, spurious beats due to oscillation signals or beat signals are not generated.

Furthermore, when the oscillation frequency of the oscillation circuit 27 becomes higher, the rising period of the time base signal supplied to the gate circuit 37 becomes shorter, and the number of input pulses supplied to the counters 34 to 31 decreases. Therefore, as is clear from FIG. 4, the count result becomes larger, and the frequency of the signals displayed by the display elements 54 to 51 becomes higher.

However, at this time, as the oscillation frequency from the oscillation circuit 27 becomes higher, the frequency of the first local oscillation signal from the VCO 21 also becomes higher, so the actual reception frequency also becomes higher.

Therefore, even if the actual receiving frequency changes due to a change in the oscillation frequency of the oscillation circuit 27, the receiving frequency and the displayed frequency change in the same direction, reducing the error between the displayed frequency and the actual receiving frequency. can.

That is, the received frequency can be digitally displayed with high precision.

In the above description, the second frequency conversion is of an upper heterodyne type, but in the case of a lower heterodyne type, the counter device 30 may be of an up-counting type.

[Brief explanation of the drawing]

FIG. 1 is a system diagram of an example of the present invention, and FIGS. 2 to 4 are diagrams for explaining the same. 12 is a VFO 120 and a PLL 130 is a counter device.

Claims (1)

[Claims] I PLL 20, VFO 12, mixer circuit 5,
The PLL 20 has a counter device 30, and the PLL 20 has a VCO
21, another mixer circuit 22, a frequency divider circuit (24 or 25), and a phase comparator circuit 26. A reference fixed oscillation circuit 27 is provided, and the oscillation signal of the VFO 12 and the oscillation signal of the VCO 21 are supplied to the another mixer circuit 22 to extract the beat signal of the two oscillation signals, and this beat signal is The signal is supplied to the phase comparison circuit 26 through the frequency dividing circuit (24 or 25) for phase comparison with the oscillation signal of the fixed oscillation circuit 27, and the phase comparison output is supplied to the VCO 21 as a control voltage to oscillate the VCO 21. The signal is supplied to the mixer circuit 5 as a local oscillation signal, and the received signal is converted into an upper heterodyne (
or lower-heterodyne) to convert the frequency into an intermediate frequency signal, and the counter device 30 includes a plurality of counters 31 and 32 to which count inputs are supplied in series.
．． . . . and a plurality of latch circuits 41, 42 . . . , which respectively latch the counter outputs. . . . and multi-digit digital display elements 51, 5 that display the latch outputs, respectively.
2. ...and the above counters 31, 32. . type),
The oscillation signal of the VFO 12 is supplied to the gate circuit 37 as a count input, and the another frequency dividing circuit 38
The frequency-divided output of the counters 31, 32 . . is supplied to the gate circuit 37 as a time base signal. . . . performs down counting (or up counting), and also outputs the time base signal, particularly the reset circuit 39.
According to the above counters 31, 32. . . are reset to the predetermined values and the digital display elements 51, 52, .
This is a super receiver that displays the received frequency digitally.