JPS609378B2 - frequency synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency synthesizer suitable for a local oscillation circuit of a superheterodyne receiver, and in particular, a phase-locked loop (PLL) constituting the frequency synthesizer has a variable division ratio prescaler type. The present invention relates to a frequency synthesizer, characterized in that the frequency synthesizer is configured to have a correcting means for digitally displaying a received frequency.

Generally, a PLL uses the method shown in Figure 1, in which the output of a voltage controlled oscillator and the output of a reference frequency oscillator are compared in frequency and phase for each reference frequency h using a phase comparator, and the PLL is synchronized. It is built like this.

When the frequency oscillated by the voltage controlled oscillator is too high to be followed by the programmable frequency divider, a prescaler type PLL as shown in FIG. 2 is employed.
However, in this method, the reference frequency f applied to the phase comparator
Since r also needs to be divided by the frequency division ratio P used in the prescaler, and comparison is made for each h/P, the time interval for phase control is shorter than in the method of comparing for each h shown in Figure 1. It is undesirable from the point of view of the S/N ratio of the PLL loop system that the output voltage fluctuation is reduced to 1/P and the output voltage fluctuation in the reduced monkey wave device is worsened by P times, the accuracy is lowered, and the reference frequency is lowered. In order to overcome this drawback, a prescaler system having a variable frequency division ratio as shown in FIG. 3 has been proposed.
That is, when the PLL is synchronized, depending on the oscillation frequency of the voltage controlled oscillator, if the division ratio of the programmable frequency divider is N, the range = N · fr ... {1)
Here, N is the frequency division ratio P of the prescaler.
, the division ratios of the two programmable frequency dividers are A,
Assuming B, N=B・P0A
...[21], and further modifying the formula to NiB P + A 10 Misaki - Misaki = (B - A) P 10 A (10 P) ... [3', then the oscillation frequency of the voltage controlled oscillator and other rotations = {( B-A)P
10A (10P)}fr...[4]

That is, the frequency division ratio of the prescaler is configured to be variable between P and P+1, and first, the frequency division ratio of the prescaler is set to P+1,
After A division with one programmable frequency divider, if the prescaler division ratio is switched to P and the other programmable frequency divider further divides B-A, it is possible to compare the phases for each reference frequency h even with the prescaler method. I understand. By the way, in a superheterodyne receiver, if the intermediate frequency is fi, then there is a gap between the receiving frequency N and the local oscillation frequency fc.
There is a relationship such as o + fi N・fr ten fi...■.

This shows that the reception frequency fa is not proportional to the value of the frequency division ratio N of the programmable frequency divider, and always deviates by the intermediate frequency fi. This frequency shift must be corrected from the viewpoint of reception frequency display, etc. That is, it is preferable that the received frequency be displayed in accordance with the change in N.
Therefore, the present invention has been devised in view of this point, and provides a frequency synthesizer configured with the aforementioned variable prescaler one-type PLL and equipped with correction means for digitally displaying the received frequency. Embodiments of the present invention will be described below with reference to FIGS. 4 and 5.

1 is a voltage controlled oscillator, 2 is a brisket whose frequency division ratio is switched to P and P+1 by coincidence signals S, S2, which will be described later.
3 is composed of a down counter and is a programmable frequency divider with a minute ratio A that takes the output of the prescaler 2 as an input, and 4 also consists of a down counter that takes the output of the prescaler 2 as an input via the pulse control circuit 5. This is a programmable frequency divider with a frequency division ratio B, and the minute ratio B is set to be larger than the frequency division ratio A.

The pulse control circuit 5 functions to apply twice as many pulses to the other programmable frequency divider 4 when the boro signal S3 is generated from one of the programmable frequency dividers 3.
6 is a phase comparator that compares the frequency and phase of the divided output of the voltage controlled oscillator 1 and the output of the reference frequency oscillator 7 which oscillates at a frequency fr equal to the inter-office frequency of the receiving band;
Reference numeral 8 denotes a low frequency converter that converts the output of the comparator 6 into a DC voltage for controlling the voltage controlled oscillator 1, and these constitute a PLL.

9 and 1 are frequency division ratio setting means connected in parallel to the programmable frequency dividers 3 and 4 and configured to set reception frequency data, and when a coincidence signal S2 is generated, the programmable frequency divider 3,
4. Reset the received frequency data.

11 and 12 are connected to the outputs of correction number setting means 13 and 14 having intermediate frequency data set to one input, and the outputs of the programmable frequency dividers 3 and 4 are connected to the other input. These are coincidence detection circuits that generate coincidence signals S, , S2 when the values match, and these constitute a programmable frequency dividing means.

A display 15 digitally displays the received frequency.

Next, regarding the operation of the present invention having such a configuration, the lower heterodyne type F. The case of M broadcast reception will be explained.
First, for example, 76. The operation of receiving a station at a lower MHZ will be explained. At this time, the voltage controlled oscillator 1 needs to oscillate at 66.2 MHZ, and since the reference frequency h' is 100 KHZ, the frequency must be divided by 662 as a programmable frequency divider. Therefore, the correction number setting means 13 and 141 respectively set 10 and 7 corresponding to the intermediate frequency of 10.7MH2, and the frequency division ratio setting means 9 and 10 respectively set 76.7MH2 of the reception frequency. 76 and 9 are respectively set corresponding to the MHZ. It is assumed that the frequency division ratio of the prescaler 2 can be switched between 10 and 11. Under such condition settings, the oscillation frequency of the voltage controlled oscillator 1 is first divided by 11 by the prescaler 2, and pulses are input to the programmable frequency dividers 3 and 4. At this time, one of the programmable frequency dividers 3 counts down from the set value of 9, and the coincidence detection circuit 12
When counting down by 2 to 7 inputted from the correction number setting means 14, the coincidence detection circuit 12 outputs a coincidence signal S,
is generated, and the splitting ratio of the prescaler 2 is switched to 10. At this time, the other programmable frequency divider 4 also has a set value of 76.
I counted down 2 from then to 74. Even after the prescaler 2 switches the frequency by 1, the other programmable frequency divider 4 continues counting down by 64 until the coincidence detection circuit 11 detects a coincidence. When the count is down by 64, a coincidence signal S2 is generated, and the prescaler 2 is switched to frequency division by 11 again, and the programmer full frequency dividers 3 and 4 are again preset to 769, which is the reception frequency.

As a result, the frequency division ratio by programmable frequency dividers 3 and 4 is:
From the above formula '41, 64×102×11=662. Therefore, the oscillation frequency of voltage controlled oscillator 1 is 66
2×100KHz=66.2MH2, 76. $M
The HZ station can be received, and the display 15 indicates that the receiving frequency is 76.
．． Insect MH2 is displayed. Next 80. A case will be explained in which a station with a low frequency of HZ is received.

In this case, since one programmable frequency divider 3 counts down from 0, a borrow occurs and a borrow signal S3 is generated. When this pollo signal S3 is generated, the pulse control circuit 5 is driven and the other programmable frequency divider 4 is slowly controlled so as to apply two pulses. That is, when the frequency is 80.0 MHz, the local oscillation frequency needs to be 69.3 MHz, and one programmable frequency divider 3 counts down by 3 from 0 to 7 to generate a match signal S. At this time, since twice as many pulses are applied to the other programmable frequency divider 4 by the action of the pulse control circuit 5 when the borrow signal S3 is generated, it becomes 76, which is down-counted by 4 from 80. Then, as described above, when the coincidence signal S, is generated, Briskeller 2 becomes 1
The programmable frequency divider 4 will count down by 66 from 76 to 10 when a match is detected, and the division ratio will be 66 x 10 3 x 11 =
It becomes 693. Therefore, voltage controlled oscillator 1 is 69.3
Can oscillate MHZ80. Stations on dish MH2 may be received. The above explanation was for the lower heterodyne system, but in the case of the upper heterodyne system, the same effect can be achieved by setting the corresponding values in the correction number setting means 13, 14', 107, or the complement value. Can be received.

Furthermore, in the above explanation, the programmable frequency dividers 3 and 4 were configured with down counters, but as shown in FIG. If it is configured so that frequency data can be preset, and further configured to compare the values of the frequency division ratio setting means 9 and 10 with the values of the programmable frequency dividers 3 and 4 and detect a match, it can also be configured as an up counter. can. At this time, if the least significant digit of the reception frequency is 0, a carry occurs in one of the frequency dividers 3, but if corrected by the pulse control circuit 5 as described above, the reception frequency will be received over all reception frequencies in the reception band. It is possible. As mentioned above, the frequency synthesizer of the present invention can correct the deviation between the local oscillation frequency and the received frequency and digitally display the received frequency in a variable division ratio prescaler type PLL, and has extremely great industrial value. .

[Brief explanation of the drawing]

1, 2, and 3 are block diagrams showing the synthesizer system, FIG. 4 is a block diagram showing the present invention, and FIG. 5 is a diagram showing another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Voltage controlled oscillator, 2...Variable division ratio prescaler, 3, 4...Programmable frequency divider, 5...Pulse control circuit, 6... . . . Phase comparator, 7 . . . Reference frequency oscillator, 8 .
, 12... Coincidence detection circuit, 13, 14...
Correction number setting means, 15...Display device. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] 1. A phase periodic loop having a variable division ratio prescaler (
In a frequency synthesizer configured with a PLL, the programmable frequency dividing means includes two programmable frequency dividers, a frequency division ratio setting means, a correction number setting means, and the frequency dividing means provided corresponding to the frequency dividers, respectively. The prescaler is configured with a detection circuit that detects that the frequency has been divided to a predetermined value, and when the prescaler is operating at one frequency division ratio and a borrow or carry occurs in one of the programmable frequency dividers, A frequency synthesizer characterized in that the frequency is divided by the other programmable frequency divider by an amount corresponding to a borrow or a carry, and the frequency division ratio of the prescaler is switched when the detection circuit detects the frequency. 2. The frequency synthesizer according to claim 1, wherein reception frequency data is set in the frequency division ratio setting means and intermediate frequency data is set in the correction number setting means.