JPS583615B2 - Shingouno Jiyujiyuhoushiki - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal exchange system for a pulse transmission line having at least two signal generation sources.

Conventionally, in a pulse transmission line with two signal generation sources, the first
Signals were exchanged using the method shown in Figure 2 or Figure 2.

That is, in FIG. 1, two signal generation sources 1 and 2 and a reception circuit 3 are independently coupled by transmission lines 4 and 5, and the outputs of signal generation sources 1 and 2 are connected to the reception circuit 3. NOR
A logical sum is obtained at gate 8, and this becomes a flip-flop 100 set input via inverter 9.

6 and 7 are terminating resistors, td1 and td2 represent the delay times of the transmission lines 4 and 5, and tdG1 and tdG2 represent the delay times of the NOR gate 8 and inverter 9.

On the other hand, in FIG. 2, the signal generation source 1 is connected to another signal generation source 2 via a transmission line 11, and the signal generation source 2 is connected to the receiving circuit 3 via one transmission line 4. In this case, , the logical sum output of the signal generation sources 1 and 2 is directly applied to the flip-flop of the receiving circuit 3 through the transmission line 4.

As in FIG. 1, 6 represents a terminating resistor, and td1 and td3 represent delay times of transmission lines 4 and 11.

By the way, in the system shown in FIG. 1, when a logic element such as a TTL element in which the polarity of the output signal is inverted with respect to the input signal is used, the polarity of the output signal from the signal generation sources 1 and 2 is changed to the S of the flip-flop 10. Even if the polarity is negative, which is the same as the polarity of the input terminal, when the logical sum is calculated using the NOR gate 8, it becomes a positive polarity signal, so the polarity must be reversed using the inverter 9. This will affect the operation of the receiving circuit 3. is the delay time of NOR gate 8 and inverter 9 tdG t + tdG
I'll be 2 minutes late.

Furthermore, if this is used in a data system that handles many signals, the number of circuit elements such as the NOR gate 8 and the inverter 9 will increase, which is undesirable.

On the other hand, in the method shown in FIG.
2 and the receiving circuit are wired in series, which eliminates the disadvantages of the method shown in Figure 1. However, there is a limit to the wiring length between signal generation source 1 and signal generation source 2, so signal generation source 1
It cannot be used if the signal generation source 2 and signal generation source 2 are far apart.

Furthermore, even if this method can be applied, the delay time from the signal generation source 2 to the flip-flop 10 of the receiving circuit 3 is td 1
+ td 3.

SUMMARY OF THE INVENTION An object of the present invention is to provide a signal exchange system that eliminates the above-mentioned drawbacks of the conventional system and minimizes the signal delay time of a pulse transmission line having two signal generation sources.

Hereinafter, the content of the present invention will be explained in detail with reference to Examples.

FIG. 3 shows an embodiment of the present invention.

That is, the present invention provides a pulse transmission line having two signal generation sources 1 and 2, in which a terminating resistor 6 is used to terminate the transmission line.
, 7 are provided on each signal generation source side, and on the reception circuit side of 3, the transmission lines 4 and 5 from each signal generation source 1 and 2 are connected to perform a logical sum, and the signal is sent to the next flip-flop circuit 10. It is characterized by the fact that

For example, signal generation sources 1 and 2 are memory stacks,
The flipflop 10 is a register that temporarily latches data read from the memory stack.

In this case, each memory stack is activated at a certain time interval (cycle time Tc in FIG. 4), and therefore the data in each memory stack is also read out periodically.

Flip-flop 10 is reset by a reset signal (not shown) in between.

FIG. 4 shows the operation timing of FIG. 3.

First, assume that the pulse signal 12 shown in FIG. 4 from the signal generation source 1 becomes "1" at time to.

This pulse signal 12 travels through the transmission line 4 having a characteristic impedance Z0 and a delay time td1, and arrives at the receiving circuit 3 as a pulse signal 13 at time t1.

Time t1 is t. It is td1 after.

The transmission line 4 is connected to the receiving circuit 3 by connecting the S input terminal of the flip-flop 10 and the transmission line 5 in series or by connecting the flip-flop 1
Since the connection to the S input terminal of the flip-flop 10 is short and the parallel wiring is done to the extent that reflection can be ignored, the pulse signal 13 is directly applied to the S input terminal of the flip-flop 10 without being reflected, and the flip-flop 100 is set.

After that, the characteristic impedance ZO is changed by the pulse signal 13.
, the pulse signal 14 is transmitted through the transmission line 5 with a delay time td2 and appears in the signal generation source 2 at time t2, but the signal generation source 2 is not operated at this time, and the termination is equal to the characteristic impedance Z0. Since the resistor 7 is connected, the pulse signal 14 is terminated at the terminating resistor 7 and no reflection occurs, and the reflected wave returns to the transmission line 5 and oscillates, so that it does not affect the next cycle.

Similarly, if the signal generation source 2 operates at time t3 after the cycle time Tc and the pulse signal 14 becomes "1", the pulse signal 1 is transmitted through the transmission line 5 and at time t4 after td2.
3 arrives at the receiving circuit 3 and is applied to the S input terminal of the flip-flop 10, where it is set.

Thereafter, the pulse signal 12 appears at time t5 in the signal generation source 1 via the transmission line 4, but the signal generation source 1 is not operated at this time, and a terminating resistor 6 equal to the characteristic impedance Z0 is connected. Therefore, the pulse signal 12 is terminated at the terminating resistor 6 and no reflection occurs, and the reflected wave does not return to the transmission line 4 and vibrate to affect the next cycle.

As is clear from the above description, according to the present invention, pulse signals from at least two signal generation sources are transmitted to the circuit to which they are transmitted only after being delayed by the delay time of each transmission line connected to the receiving circuit. It becomes possible to convey.

That is, the delay time of the NOR gate 8 and inverter 9 in FIG. 1 and these circuit elements can be eliminated, and the length limit and delay time td3 of the transmission line 11 in FIG. 2 can be eliminated.
can be eliminated.

[Brief explanation of drawings]

1 and 2 are conventional examples of the signal transfer method between two signal generation sources and a receiving circuit, FIG. 3 is an example of the signal transfer method of the present invention, and FIG. 4 is the same as that shown in FIG. FIG. 3 is a diagram showing operation timing. 1, 2... Signal generation source, 3... Receiving circuit, 4, 5... Transmission line, 6, 7... Termination resistor.

Claims (1)

[Claims] 1. In a signal exchange method in which at least two signal generation sources are connected to one reception circuit via individual transmission lines, and the reception circuit sequentially receives signals output from each signal generation source at different timings, A signal transmission/reception method characterized in that a terminating resistor for terminating a line is provided on each signal generation source side, and each transmission line is connected to form a logical phase on the input side of the receiving circuit.