JPS5833869A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve operating speed of an element which is disposed in three dimensions and to increase the integration of a semiconductor device by connecting the element via a low resistance wire pattern, thereby decreasing the wiring capacity. CONSTITUTION:After an N type diffused layer 2 is formed on the main surface of a P type substrate 1, an N type first vapor growth region 3 is formed. A diode 5, a transistor 6 and a resistor 7 are respectively formed in isolated vapor growth layers 3', 3'', 3''' via P type diffused layers 4, 4', 4'' in the region 3. An aluminum or aluminum alloy series first wire pattern 9 is formed through the first insulating layer 8 on the layer 3, and are suitably connected to the layer 3. Subsequently, the second insulating layer 10 is formed on the upper surface. Then, the second vapor growth region 11 is formed on the upper surface, and a transistor 11' and a diode 11'' are formed. Further, similar formation is repeated, thereby forming the third and other layers which follow.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a modified structure for increasing the degree of integration of a semiconductor device.

Semiconductor integrated circuit device: A plurality of active elements are formed on a semiconductor substrate using oxidation diffusion technology and microfabrication technology (various ring processing techniques). A method of wiring using silicon or a compound of metal and silicon is used. It is preferable that the wiring resistance be as low as possible, and it becomes a serious factor especially in high-speed operation devices or bipolar devices with a large operating current. Therefore, in an integrated circuit device having such an element, a low resistance wiring of less than 0.03Ω is required, and currently aluminum and aluminum alloys are mainly used as wiring materials.

However, these metals have low melting points and cannot be subjected to high-temperature (approximately 500° C. or higher) processes after forming wiring, so it has not been possible to form another O element on top of wiring.

On the other hand, polycrystalline silicon, high melting point metals (Mo, W,
Wiring made of TIW, Ta), etc. can withstand high temperatures well, and it is common practice to form another element on top of the wiring with an insulating film interposed therebetween. This technology is detailed in the following literature.

[A New Polyslicon Process
s for a BipolarDevices-P
S A Tehnology, K, 0KADA
et ml, : IEEE Trans, on
Electron Devices, Vol, E-2
6°No, 4th pril 1979. However, the electrical resistance of the above materials is more than an order of magnitude higher than that of aluminum, which limits the types of devices that can be used, and has serious drawbacks such as insufficient characteristics in terms of operating speed and the like.

Due to the above-mentioned circumstances, the arrangement of each element has conventionally been limited to the surface of the substrate, resulting in a limit to the number of elements per unit area. Furthermore, recently there has been a demand for an increase in the number of functions per chip, so in order to meet this demand it is necessary to increase the area of the chips that make up the elements. There are drawbacks such as many problems in terms of electrical characteristics due to the length of the wiring.

The present invention provides a semiconductor device structure that improves the above-mentioned conventional drawbacks.

A semiconductor device according to the present invention includes a semiconductor substrate, a vapor-phase grown semiconductor layer that is insulated from each other by an electrically insulating layer, and an active element, a passive element, and a low-melting-point, low-resistance wiring layer. The method is characterized in that a desired connection is made between the wiring layers or between the wiring layer and the vapor-phase grown semiconductor layer.

Next, try this invention! Bipolar of J case (2nd with Moss)
Although the bipolar integrated circuit shown in the figure (FIG. 2 is a circuit diagram) shows wiring up to the third layer and omits the others, it is also possible to obtain a multilayer structure by repeating the same structure. In the figure, (1) is a substrate of P conductivity type (hereinafter abbreviated as P type), and diffusion of N conductivity type (hereinafter abbreviated as N type) to form a buried layer later on a part of one main surface. After providing the layer (2), a first vapor growth silicon region (hereinafter abbreviated as vapor growth region) (3) of Nu is formed. This first vapor phase growth region (31 has a partially provided P deaf diffusion layer (4J,
A diode (5) is connected to the vapor growth layer (3'), (3"), (3") separated by
), a transistor (6), and a resistor (73) are formed, and each of these has a diode (5) connected to a 7 node [J
iR (5m),) base area (6b) on transistor (6)
), the resistor (7) and the K resistance region (7r) are each formed of a P deaf diffusion layer. Further, in the same way as the formation of the P-type diffusion layer, the N-type diffusion layer partially formed is a diode (5
), an emitter region (6.) and a collector (lead-out) region (6c) of the transistor (6), etc. Next, a first wiring pattern (9) of aluminum or an aluminum-based alloy is formed via a first insulating layer (8) deposited on the surface of the first ζO vapor growth layer.

Next, a second insulating JIIQ (I) layer such as StO or Si3N is deposited on the upper surface by plasma vapor deposition to a thickness of approximately 1.
Formed to 0 μm. After forming the first wiring pattern, the upper limit is set at 500°C in order to prevent thermal damage to this pattern, for example, if the wiring pattern is made of aluminum, so plasma vapor deposition is used for vapor phase growth. In addition, ion implantation is used for the subsequent implantation of the diffused impurity, and electron beam annealing is used instead of laser for annealing. The above plasma vapor phase growth is performed at a formation temperature [300°C, SIH
, H = 0.5, generation pressure 0.2) Torr
), RF power of 500 W, preferably using parallel plate electrodes.Then, the second insulating layer is annealed by a laser annealing method. This laser annealing was performed in an argon atmosphere with an output of 6W, a beam diameter of 40μ, and a scanning speed of [1051/
After applying the see, patterning is applied to form contact through holes. Next, amorphous silicon is deposited on this upper surface by plasma vapor deposition to a layer thickness of, for example, 0.5.
A second vapor phase growth region αυ of the μ area is formed. The above plasma vapor phase growth method is carried out using 8iH4 at a formation temperature of f300° C., a formation pressure of 0.2 Torr, an RF power of 0, and parallel plate electrodes. Next, the second gas phase member region was subjected to photophosphorography (Ph@teli th@graphy) method and photophrographic method (y v t y CF410t).
) A large number of island regions (11') each having a size of 3 X Is to 3
impurities (e.g. B), also aNII impurities (e.g. P,
(S, etc.) is implanted, and the impurities are activated and each island region is made into a single crystal by laser annealing. The above laser annealing conditions may be, for example, a CW-MR laser output IOW, a beam spot diameter of 4011 m5, and a scanning speed of about 0.3 m/see.

In this way, the element formed in the second vapor phase growth region can be formed into an element having the same characteristics as the element formed in the first vapor phase growth region.

Next, j! of this II2 vapor phase growth region! A second insulating layer (
A second wiring pattern 0 of aluminum or aluminum thread alloy is formed via II. Note that one of the above island regions (11') is a PNP transistor, and its (lie
') is the collector area, (ltb') is the base area, (1
1@') is the emitter region, and its collector region is the array */
It penetrates through the insulating layer by an e-turn and is connected to the base region (6b) of the transistor in the first vapor phase growth region. 9, and the other island region (11") is the anode region (
A diode in which a canode region (ll/) and a canode region (llkl) are formed, and a canode region (ll/) is formed. The resistance layer (7) of the first vapor phase growth region is formed by penetrating the insulating layer
r).

Further, layers g3 and subsequent layers can be formed repeatedly in the same manner as the formation of the second layer element. In addition, in FIG. 1, up to the third dove is shown, in which the diode is formed by the insulating layer, the wiring pattern, and the island region. The circuit of the IC formed in this way is as shown in No. 2-0. 9. Figures 3 to 6 show a moss type element (!!13), a diode (Figure 4), and a diode (Figure 4) formed in the vapor phase growth region after the second layer.
Each basic structure of a bipolar type element (Figures 5 and 6) is illustrated, and in each figure, gloss is an insulating layer, (31m) is an unsu region, (31 reef) is a drain region, and (31g) is a gate F region. , 01 is a wiring pattern, and in FIG. 6, it is formed so that the collector electrode is led out from the bottom.

According to this invention, the total number of elements increases to approximately 7000.Bipolar/MOS coexistence 2Pt11. The device has been formed.

It is preferable that the linear circuit is mainly placed on the substrate, and the logic circuit is mainly placed on the 2N1 position. A comparison of this invention with the conventional technology is as shown in the following table. In II, A is 1'
The area of the 1L element and B indicate the minimum propagation delay time (7-stage ring oscillator: logic section, N-channel MOS transistor).

As stated above, according to the present invention, by connecting three-dimensionally arranged elements with a low-resistance wiring pattern, the operation speed of the elements can be improved dramatically as the wiring capacitance O decreases. We can expect an increase in the degree of integration.

[Brief explanation of drawings]

Figure 1 is a sectional view of one embodiment of the present invention, Figure 2 is a circuit diagram formed by the IC of Figure 1, and Figures 3 to 6 are elements for further explaining the device of this invention. 6 in a cross-sectional view. l Silicon substrate 3 First vapor growth region 5.11", 21 Diode 6
Transistor 7 Resistor' 8.10, 20, 30 Insulating layer 9.19, 29, 39 Wiring pattern 11'
MOS Transistor Representative Patent Attorney Inoue - Male Figure 2

Claims (2)

[Claims] (1) An active element, a passive element, and a low-melting-point, low-resistance wiring layer are disposed on a semiconductor substrate and are insulated from each other by an electrically insulating layer, and an in-film conductor layer is provided, and between the wiring layers or Desired O! between the wiring layer and the semiconductor layer! A semiconductor device characterized by being provided with an I-line. (2) The semiconductor device according to claim S, wherein the wiring layer is made of metal.