JPS5832511B2 - vertical field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a vertical field effect transistor, and more particularly to a vertical field effect transistor with significantly reduced junction capacitance.

Conventional vertical field effect transistors are known as vertical die-carving effect transistors that exhibit triode characteristics.
As shown in the figure, a high resistivity layer 2 containing impurities of the first conductivity type is formed by epitaxial growth on a semiconductor substrate 1 containing impurities of the first conductivity type and serving as a drain region. A net-shaped gate region 3 containing impurities of the first conductivity type is formed by diffusion, a channel region 4 is formed, and a low resistance source region 5 containing impurities of the first conductivity type is further formed on the high resistivity layer 2. Formed by epitaxial growth.

Next, after forming a region 6 having the second conductivity type impurity and a low resistance source region 7 having the first conductivity type impurity for taking out the gate electrode, the gate electrode 8, the source electrode 9, and the drain electrode 10 are formed. It is obtained by coating.

However, the vertical field effect transistor formed as described above has a drawback in that the junction capacitance is large and high frequency characteristics cannot be improved.

In particular, high-power devices have a large junction capacitance and are currently used mostly in the audio frequency range.

Needless to say, for audio applications, it is advantageous to have as small a capacity as possible in terms of sound quality, circuitry, etc.

Specifically, it is approximately 700 pF to 800 p with a 5-way element.
F is also present, and its large junction capacitance is a major reason why the range of application of vertical field effect transistors is narrow.

The present invention has been made in view of this point, and provides an element with significantly reduced junction capacitance.

The manufacturing process of the n-channel vertical field effect transistor of the present invention will be explained below with reference to FIG.

First, as shown in FIG. 2a, an N-type semiconductor 2 with a high specific resistance is formed by epitaxial growth on an N-type semiconductor substrate 1 with a low resistance of, for example, about 0.01Ω to 0.001Ωcm, which will eventually become a drain region. do.

Next, as shown in FIG. 2, an impurity imparting P type is selectively diffused into a predetermined portion of the high resistivity semiconductor layer 2 to form a channel between the net-shaped first gate region 3 and each first gate region 3. Region 4 is formed.

Next, as shown in FIG. 2C, N-type epitaxial growth is performed on the high resistivity semiconductor layer 2 including the first gate region 3 to a thickness of 5 to 15 μm to form an N-type semiconductor layer 5.

Next, as shown in FIG. 2d, an oxide film 12 is formed on the semiconductor surface, and then a predetermined portion of the oxide film 1 is formed using photolithography.
2 is removed to open a window 13 for selective diffusion.

Through this window 13, an impurity imparting P-type conductivity is not connected to the first gate region 3 but is diffused to a position close to it to form the second gate region 11.

Specifically, the distance between the first gate region 3 and the second gate region 11 is such that the depletion layer from the second gate region 11 has already reached the first gate region 3 at zero bias, that is, 2 μ~ 6μ is appropriate.

Next, as shown in FIG. 2e, an N+ source region 7 for making a source contact is formed in the N-type semiconductor layer 5, and then the N+ source region 7, second gate region 11 and drain region 1 are formed. Source electrode 9 and gate electrode 8, respectively.
, the drain electrode 10 is deposited to obtain the desired vertical field effect transistor.

In an element having such a structure, when a reverse bias is applied between the gate electrode 8 and the source electrode 9, the depletion layer extends from the junction of the second gate region 11 and reaches the adjacent first gate region 3.

When the depletion layer reaches the first gate region 3, an electric field is applied in a direction that cancels out the electric field from the second gate region 11, that is, the depletion layer also extends from the junction of the first gate region 3.

This is based on the same principle as the guard ring structure for achieving high voltage resistance.

It is no problem even if the depletion layer from the second gate region 11 has already reached the first gate region at zero bias.

In this way, the electric field in the first gate region 3 changes in accordance with the strength of the electric field in the second gate region 11, and the conductivity of the channel region 4 changes accordingly, so that operation as a field effect transistor can occur.

On the other hand, the gate-source capacitance CG, s and the gate-drain capacitance COD are mostly determined by the junction area of the second gate region 11, and the contribution of capacitance by the junction of the first gate region 3, which occupies most of the gate region, is small. .

Therefore, the gate-source junction capacitance CGS and the gate-drain junction capacitance COD are significantly reduced.

According to the results of the prototype, the voltage amplification rate is about 8 with a 5M[] die.
The device has a gate-source capacitance CGS of 107 pF and a gate-drain capacitance COD of 107 pF.

The circuit of the present invention is equivalent to not only having a capacitor inserted into the gate input part of a buried gate field effect transistor, but also having a resistor connected in parallel to the capacitor that causes a reverse leakage current of a PN junction. It is possible, but in this case the reverse leakage current of the PN junction is very small, so the voltage drop is small. The decrease in m is slight.

As is well known, the figure of merit M, which represents the frequency characteristics of FET, is
M-1m/C15s (1m: mutual conductance, C
15s: capacitance between gate and source + capacitance between gate and drain), but in the case of the present invention, C15s is significantly reduced and '? Since the decrease in m is slight, there is an advantage that the figure of merit M becomes large.

As mentioned above, in view of the fact that the junction capacitance between the gate and the source and between the gate and the drain was large due to the large junction area of the gate region, in the present invention, the gate region is divided into a first gate region and a second gate region. However, it has the effect of causing a field effect transistor to operate on the same principle as the guard ring structure, while significantly reducing the junction capacitance.

In the above embodiments, an n-channel vertical field effect transistor has been described, but the present invention may also be applied to a p-channel vertical field effect transistor.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a conventional vertical field effect transistor, and FIGS. 2 a, b, c, d, and e are sectional views showing a vertical field effect transistor according to the present invention in the order of manufacturing steps. In the figure, 1 is a semiconductor substrate, 2 is a high resistivity semiconductor layer,
3 is a first gate region, 4 is a channel region, 5 is a buried epitaxial growth layer, and 11 is a second gate region. The same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1. In a vertical field effect transistor in which a net-shaped gate region having an opposite conductivity type is buried in a semiconductor layer of a predetermined conductivity type constituting a source/drain region to form a channel region, the net-shaped buried gate region is 1. A vertical field effect transistor, comprising a second gate region disposed adjacent to the second gate region and having the same conductivity type as the second gate region, and a gate electrode deposited on the second gate region.