JPS5829187A - キヤツシユメモリ制御装置 - Google Patents

キヤツシユメモリ制御装置

Info

Publication number
JPS5829187A
JPS5829187A JP56126581A JP12658181A JPS5829187A JP S5829187 A JPS5829187 A JP S5829187A JP 56126581 A JP56126581 A JP 56126581A JP 12658181 A JP12658181 A JP 12658181A JP S5829187 A JPS5829187 A JP S5829187A
Authority
JP
Japan
Prior art keywords
address
cache memory
instruction
operand
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56126581A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6126702B2 (uk
Inventor
Hiroyuki Nishimura
西村　弘行
Mikiya Akagi
赤木　三樹也
Hideki Nishimura
英樹 西村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56126581A priority Critical patent/JPS5829187A/ja
Priority to US06/294,121 priority patent/US4467414A/en
Priority to FR8116082A priority patent/FR2489021B1/fr
Publication of JPS5829187A publication Critical patent/JPS5829187A/ja
Publication of JPS6126702B2 publication Critical patent/JPS6126702B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP56126581A 1980-08-22 1981-08-14 キヤツシユメモリ制御装置 Granted JPS5829187A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP56126581A JPS5829187A (ja) 1981-08-14 1981-08-14 キヤツシユメモリ制御装置
US06/294,121 US4467414A (en) 1980-08-22 1981-08-19 Cashe memory arrangement comprising a cashe buffer in combination with a pair of cache memories
FR8116082A FR2489021B1 (fr) 1980-08-22 1981-08-21 Agencement d'antememoires comprenant une antememoire tampon en combinaison avec une paire d'antememoires

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56126581A JPS5829187A (ja) 1981-08-14 1981-08-14 キヤツシユメモリ制御装置

Publications (2)

Publication Number Publication Date
JPS5829187A true JPS5829187A (ja) 1983-02-21
JPS6126702B2 JPS6126702B2 (uk) 1986-06-21

Family

ID=14938709

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56126581A Granted JPS5829187A (ja) 1980-08-22 1981-08-14 キヤツシユメモリ制御装置

Country Status (1)

Country Link
JP (1) JPS5829187A (uk)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60123936A (ja) * 1983-12-07 1985-07-02 Fujitsu Ltd バッフア記憶制御方式
JPS60151749A (ja) * 1984-01-18 1985-08-09 Nec Corp 情報処理装置
JPS6116350A (ja) * 1984-07-02 1986-01-24 Nec Corp 情報処理装置のバツフア記憶装置
JPS6149250A (ja) * 1984-08-17 1986-03-11 Fujitsu Ltd バツフア記憶制御方式
JPS61245963A (ja) * 1985-04-23 1986-11-01 Toshiba Mach Co Ltd 溶湯供給装置
EP0325677A2 (de) * 1988-01-25 1989-08-02 Otto Müller Schaltungsanordnung und Steuerverfahren eines Befehlspufferspeichers in einer Datenverarbeitungsanlage
JPH0224538Y2 (uk) * 1987-10-20 1990-07-05
US6374334B1 (en) 1994-07-04 2002-04-16 Fujitsu Limited Data processing apparatus with a cache controlling device
JP2006318471A (ja) * 2005-05-09 2006-11-24 Sony Computer Entertainment Europe Ltd データ処理におけるメモリキャッシング

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63130502U (uk) * 1987-02-18 1988-08-26
JP2530511B2 (ja) * 1990-06-08 1996-09-04 統冶 石谷 構築物における添景物の形成方法

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60123936A (ja) * 1983-12-07 1985-07-02 Fujitsu Ltd バッフア記憶制御方式
JPH0526212B2 (uk) * 1983-12-07 1993-04-15 Fujitsu Ltd
JPS60151749A (ja) * 1984-01-18 1985-08-09 Nec Corp 情報処理装置
JPS6116350A (ja) * 1984-07-02 1986-01-24 Nec Corp 情報処理装置のバツフア記憶装置
JPS6149250A (ja) * 1984-08-17 1986-03-11 Fujitsu Ltd バツフア記憶制御方式
JPH0351012B2 (uk) * 1984-08-17 1991-08-05 Fujitsu Ltd
JPS61245963A (ja) * 1985-04-23 1986-11-01 Toshiba Mach Co Ltd 溶湯供給装置
JPH0224538Y2 (uk) * 1987-10-20 1990-07-05
EP0325677A2 (de) * 1988-01-25 1989-08-02 Otto Müller Schaltungsanordnung und Steuerverfahren eines Befehlspufferspeichers in einer Datenverarbeitungsanlage
US6374334B1 (en) 1994-07-04 2002-04-16 Fujitsu Limited Data processing apparatus with a cache controlling device
JP2006318471A (ja) * 2005-05-09 2006-11-24 Sony Computer Entertainment Europe Ltd データ処理におけるメモリキャッシング
JP4666511B2 (ja) * 2005-05-09 2011-04-06 ソニー コンピュータ エンタテインメント ヨーロッパ リミテッド データ処理におけるメモリキャッシング

Also Published As

Publication number Publication date
JPS6126702B2 (uk) 1986-06-21

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