FR2489021B1 - Agencement d'antememoires comprenant une antememoire tampon en combinaison avec une paire d'antememoires - Google Patents

Agencement d'antememoires comprenant une antememoire tampon en combinaison avec une paire d'antememoires

Info

Publication number
FR2489021B1
FR2489021B1 FR8116082A FR8116082A FR2489021B1 FR 2489021 B1 FR2489021 B1 FR 2489021B1 FR 8116082 A FR8116082 A FR 8116082A FR 8116082 A FR8116082 A FR 8116082A FR 2489021 B1 FR2489021 B1 FR 2489021B1
Authority
FR
France
Prior art keywords
anthemoires
antememory
anememory
buffer
pair
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8116082A
Other languages
English (en)
Other versions
FR2489021A1 (fr
Inventor
Mikiya Akagi
Hiroyuki Nishimura
Hideki Nishimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP55115533A external-priority patent/JPS6053335B2/ja
Priority claimed from JP55118627A external-priority patent/JPS6022376B2/ja
Priority claimed from JP56126579A external-priority patent/JPS5829186A/ja
Priority claimed from JP56126581A external-priority patent/JPS5829187A/ja
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Publication of FR2489021A1 publication Critical patent/FR2489021A1/fr
Application granted granted Critical
Publication of FR2489021B1 publication Critical patent/FR2489021B1/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
FR8116082A 1980-08-22 1981-08-21 Agencement d'antememoires comprenant une antememoire tampon en combinaison avec une paire d'antememoires Expired FR2489021B1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP55115533A JPS6053335B2 (ja) 1980-08-22 1980-08-22 情報処理装置
JP55118627A JPS6022376B2 (ja) 1980-08-28 1980-08-28 キャッシュメモリ制御装置
JP56126579A JPS5829186A (ja) 1981-08-14 1981-08-14 情報処理装置
JP56126581A JPS5829187A (ja) 1981-08-14 1981-08-14 キヤツシユメモリ制御装置

Publications (2)

Publication Number Publication Date
FR2489021A1 FR2489021A1 (fr) 1982-02-26
FR2489021B1 true FR2489021B1 (fr) 1986-05-09

Family

ID=27470268

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8116082A Expired FR2489021B1 (fr) 1980-08-22 1981-08-21 Agencement d'antememoires comprenant une antememoire tampon en combinaison avec une paire d'antememoires

Country Status (2)

Country Link
US (1) US4467414A (fr)
FR (1) FR2489021B1 (fr)

Families Citing this family (49)

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US4670839A (en) * 1982-09-27 1987-06-02 Data General Corporation Encachement apparatus using two caches each responsive to a key for simultaneously accessing and combining data therefrom
US4652995A (en) * 1982-09-27 1987-03-24 Data General Corporation Encachement apparatus using multiple caches for providing multiple component values to form data items
WO1984002799A1 (fr) * 1982-12-30 1984-07-19 Ibm Systeme de memoire hierarchique comprenant des antememoires pour stocker des donnees et des instructions
EP0150177A1 (fr) * 1983-07-11 1985-08-07 Prime Computer, Inc. Systeme de traitement de donnees
AU3229484A (en) * 1983-09-07 1985-03-14 Amdahl Corporation Time shared translation buffer
JPS6091462A (ja) * 1983-10-26 1985-05-22 Toshiba Corp 演算制御装置
JPS60123936A (ja) * 1983-12-07 1985-07-02 Fujitsu Ltd バッフア記憶制御方式
JPS60124754A (ja) * 1983-12-09 1985-07-03 Fujitsu Ltd バッファ記憶制御装置
JPH0644245B2 (ja) * 1983-12-29 1994-06-08 富士通株式会社 ストアバッファ装置
US4985829A (en) * 1984-07-31 1991-01-15 Texas Instruments Incorporated Cache hierarchy design for use in a memory management unit
US4648033A (en) * 1984-09-07 1987-03-03 International Business Machines Corporation Look-aside buffer LRU marker controller
US4860192A (en) * 1985-02-22 1989-08-22 Intergraph Corporation Quadword boundary cache system
JPS6297036A (ja) * 1985-07-31 1987-05-06 テキサス　インスツルメンツ　インコ−ポレイテツド 計算機システム
US4766535A (en) * 1985-12-20 1988-08-23 International Business Machines Corporation High-performance multiple port memory
US4785398A (en) * 1985-12-19 1988-11-15 Honeywell Bull Inc. Virtual cache system using page level number generating CAM to access other memories for processing requests relating to a page
AU587714B2 (en) * 1986-08-27 1989-08-24 Amdahl Corporation Cache storage queue
US4881163A (en) * 1986-09-19 1989-11-14 Amdahl Corporation Computer system architecture employing cache data line move-out queue buffer
JPH0221342A (ja) * 1987-02-27 1990-01-24 Hitachi Ltd マルチプロセッサシステム及びマルチプロセッサシステムにおける論理キャッシュメモリのアクセス方法
US5029105A (en) * 1987-08-18 1991-07-02 Hewlett-Packard Programmable pipeline for formatting RGB pixel data into fields of selected size
DE3802025C1 (fr) * 1988-01-25 1989-07-20 Otto 7750 Konstanz De Mueller
US5023776A (en) * 1988-02-22 1991-06-11 International Business Machines Corp. Store queue for a tightly coupled multiple processor configuration with two-level cache buffer storage
US5210843A (en) * 1988-03-25 1993-05-11 Northern Telecom Limited Pseudo set-associative memory caching arrangement
DE68924306T2 (de) * 1988-06-27 1996-05-09 Digital Equipment Corp Mehrprozessorrechneranordnungen mit gemeinsamem Speicher und privaten Cache-Speichern.
US5050068A (en) * 1988-10-03 1991-09-17 Duke University Method and apparatus for using extracted program flow information to prepare for execution multiple instruction streams
US5179679A (en) * 1989-04-07 1993-01-12 Shoemaker Kenneth D Apparatus and method for permitting reading of data from an external memory when data is stored in a write buffer in the event of a cache read miss
US5193166A (en) * 1989-04-21 1993-03-09 Bell-Northern Research Ltd. Cache-memory architecture comprising a single address tag for each cache memory
JPH0711793B2 (ja) * 1989-07-13 1995-02-08 株式会社東芝 マイクロプロセッサ
US5117493A (en) * 1989-08-07 1992-05-26 Sun Microsystems, Inc. Pipelined register cache
US5363486A (en) * 1989-11-13 1994-11-08 Zenith Data Systems Corporation Variable size queue circuit for buffering data transfers from a processor to a memory
EP0843254A3 (fr) * 1990-01-18 1999-08-18 National Semiconductor Corporation Processeur de traitement de signaux numériques et processeur universal intégré avec mémoire interne partagée
US5317718A (en) * 1990-03-27 1994-05-31 Digital Equipment Corporation Data processing system and method with prefetch buffers
JPH0437935A (ja) * 1990-06-01 1992-02-07 Hitachi Ltd キャッシュメモリを有する計算機
US5251321A (en) * 1990-06-20 1993-10-05 Bull Hn Information Systems Inc. Binary to binary coded decimal and binary coded decimal to binary conversion in a VLSI central processing unit
US5454093A (en) * 1991-02-25 1995-09-26 International Business Machines Corporation Buffer bypass for quick data access
GB2256512B (en) * 1991-06-04 1995-03-15 Intel Corp Second level cache controller unit and system
JPH05274273A (ja) * 1991-06-28 1993-10-22 Digital Equip Corp <Dec> コンピュータ・システムに於ける素子のインターロック・スキーム
JP3451099B2 (ja) 1991-12-06 2003-09-29 株式会社日立製作所 外部記憶サブシステム
US5771367A (en) * 1992-12-17 1998-06-23 International Business Machines Corporation Storage controller and method for improved failure recovery using cross-coupled cache memories and nonvolatile stores
US5692152A (en) * 1994-06-29 1997-11-25 Exponential Technology, Inc. Master-slave cache system with de-coupled data and tag pipelines and loop-back
US5551001A (en) * 1994-06-29 1996-08-27 Exponential Technology, Inc. Master-slave cache system for instruction and data cache memories
JP3277730B2 (ja) * 1994-11-30 2002-04-22 株式会社日立製作所 半導体メモリ装置、及び、それを用いた情報処理装置
JPH09114734A (ja) * 1995-10-16 1997-05-02 Hitachi Ltd ストアバッファ装置
US6223259B1 (en) * 1998-10-30 2001-04-24 Telefonaktiebolaget Lm Ericsson (Publ) Reducing read cycle of memory read request for data to be partially modified by a pending write request
EP1050806A1 (fr) 1999-05-03 2000-11-08 STMicroelectronics SA Comparaison d'adresse de mémoire
US6629167B1 (en) * 2000-02-18 2003-09-30 Hewlett-Packard Development Company, L.P. Pipeline decoupling buffer for handling early data and late data
JP3694005B2 (ja) * 2003-05-21 2005-09-14 沖電気工業株式会社 デジタル信号処理装置及びデジタル信号処理方法
CN101478785B (zh) * 2009-01-21 2010-08-04 华为技术有限公司 资源池管理系统及信号处理方法

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US3470540A (en) * 1967-04-24 1969-09-30 Rca Corp Multiprocessing computer system with special instruction sequencing
US3618041A (en) * 1968-10-31 1971-11-02 Hitachi Ltd Memory control system
FR111566A (fr) * 1974-10-04
US4156906A (en) * 1977-11-22 1979-05-29 Honeywell Information Systems Inc. Buffer store including control apparatus which facilitates the concurrent processing of a plurality of commands
US4217640A (en) * 1978-12-11 1980-08-12 Honeywell Information Systems Inc. Cache unit with transit block buffer apparatus
US4208716A (en) * 1978-12-11 1980-06-17 Honeywell Information Systems Inc. Cache arrangement for performing simultaneous read/write operations

Also Published As

Publication number Publication date
FR2489021A1 (fr) 1982-02-26
US4467414A (en) 1984-08-21

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Legal Events

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ST Notification of lapse