JPS5827392A - Method of plating printed board - Google Patents

Method of plating printed board

Info

Publication number
JPS5827392A
JPS5827392A JP12402081A JP12402081A JPS5827392A JP S5827392 A JPS5827392 A JP S5827392A JP 12402081 A JP12402081 A JP 12402081A JP 12402081 A JP12402081 A JP 12402081A JP S5827392 A JPS5827392 A JP S5827392A
Authority
JP
Japan
Prior art keywords
pattern
plating
mask
plated
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12402081A
Other languages
Japanese (ja)
Other versions
JPS5952556B2 (en
Inventor
利介 尾崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
OK PRINT HAISEN KK
OOKEE PURINTO HAISEN KK
Original Assignee
OK PRINT HAISEN KK
OOKEE PURINTO HAISEN KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by OK PRINT HAISEN KK, OOKEE PURINTO HAISEN KK filed Critical OK PRINT HAISEN KK
Priority to JP12402081A priority Critical patent/JPS5952556B2/en
Publication of JPS5827392A publication Critical patent/JPS5827392A/en
Publication of JPS5952556B2 publication Critical patent/JPS5952556B2/en
Expired legal-status Critical Current

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  • Manufacturing Of Printed Wiring (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 この発明はプリント基板のパターンにメッキを施す方法
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of plating a pattern on a printed circuit board.

従来、パターンにメッキを施したプリント基板を製造す
るには、まず第1図に示すように9表面に銅箔を形成し
た基板1のパターンとなる部分2および入電部分9を残
してマスク3を形成したのち、入電部分9から入電して
電解メッキを行ない部分2にメッキを施し、のちにマス
ク3を除去しつぎにメッキをレジストとしてエツチング
を行なっている。
Conventionally, in order to manufacture a printed circuit board with a plating pattern, first, as shown in FIG. After the formation, electrolytic plating is performed by applying electricity from the current input portion 9 to plate the portion 2. Afterwards, the mask 3 is removed and etching is then performed using the plating as a resist.

しかしながら、この方法においては、パターンの一部に
メッキを施すことができないから、メッキを施す必要が
ないパターンにもメッキが施されるので、たとえば金メ
ッキなどの場合には、コストが非常に高くなる。また、
メッキをレジストとしてエンチングを行なうから、メッ
キのオーバーハングが生ずるので、オーバーハングした
部分が剥離して、ブリッジ等の事故が生ずるおそれがあ
る。さらに、パターンのエツチングサイド面にはメッキ
が施されないので、パターンが腐食されることがある。
However, in this method, it is not possible to plate a part of the pattern, so patterns that do not need to be plated are also plated, so the cost becomes very high, for example, in the case of gold plating. . Also,
Since etching is performed using plating as a resist, overhang of the plating occurs, and there is a risk that the overhanging portion will peel off and cause accidents such as bridging. Furthermore, since the etched side surfaces of the pattern are not plated, the pattern may be corroded.

この発明は上述の問題点を解決するためになされたもの
で、パターンの一部にメッキを施すことができ、メッキ
のオーバーハングが生ずることがなく、さらにパターン
のエツチングサイド面にもメッキを施すことができるプ
リント基板のメッキ方法を提供することを目的とする。
This invention was made to solve the above-mentioned problems, and it is possible to plate a part of the pattern without causing overhang of the plating, and also to plate the etched side surface of the pattern. The purpose of the present invention is to provide a method for plating a printed circuit board.

この目的を達成するため、この発明においては両面に導
体膜が形成され、上記両面の導体膜がスルホールの内面
に設けられた導体によって導通された基板の第1面にの
みパターンを形成し、つぎに上記パターンのメッキを施
す部分を残して上記第1面にマスクを形成するとともに
、上記基板の第2面にマスクを形成して、電解メッキを
行ない上記パターンのメッキを施す部分にメッキを施し
つぎに上記第1面の全面にマスクを形成して、上記第2
面にパターンを形成する。
In order to achieve this object, in the present invention, conductor films are formed on both sides, and a pattern is formed only on the first surface of the substrate where the conductor films on both sides are electrically connected by the conductor provided on the inner surface of the through hole. A mask is formed on the first surface, leaving a portion to be plated in the pattern, and a mask is formed on the second surface of the substrate, and electrolytic plating is performed to plate the portion to be plated in the pattern. Next, a mask is formed on the entire surface of the first surface, and the second surface is covered with a mask.
Form a pattern on the surface.

第2図ないし第8図はこの発明に係るプリント基板のメ
ッキ方法の説明図である。まず、第2図第6図(第2図
のA −A、断面図)、第4図に示すように0両面に導
体膜4が形成され9両面の導体膜4がスルホール5の内
面に設けられた導体6によって導通された基板7の第1
面(第2図に示す面)にのみパターン8を形成し、第2
面(第4図に示す面)にはパターンを形成しない。すな
わち第1面のパターンとなる部分にレジストを形成し第
2図の全面にマスクを形成したのちに、エツチングを行
ない、レジスト、マスクを除去し、パターン8を形成す
る。つぎに、第5図に示すようにパターン8のメッキを
施す部分8aを残して第1面にマスク10を形成すると
ともに、第6図に汗すように・、第2面に入電部分9を
残してマスク11を形成したのち、入電部分9から入電
して電解メッキを行ない、メッキを施す部分8aにメッ
キを施し、のちにマスク10.11を除去する。
FIGS. 2 to 8 are explanatory diagrams of a printed circuit board plating method according to the present invention. First, as shown in FIG. 2, FIG. 6 (cross-sectional view taken along line A-A in FIG. 2), and FIG. The first conductor 7 of the substrate 7 is electrically connected by the conductor 6
The pattern 8 is formed only on the surface (the surface shown in FIG. 2), and the second
No pattern is formed on the surface (the surface shown in FIG. 4). That is, after a resist is formed on a portion of the first surface that will become a pattern and a mask is formed on the entire surface as shown in FIG. 2, etching is performed to remove the resist and mask, and pattern 8 is formed. Next, as shown in FIG. 5, a mask 10 is formed on the first surface, leaving a portion 8a to be plated with a pattern 8, and as shown in FIG. After forming a mask 11 by leaving a portion of the mask 10, electrolytic plating is performed by applying electricity from the current input portion 9, plating is applied to the portion 8a to be plated, and the mask 10.11 is removed later.

この場合、メッキを施す部分8aはパターン8゜導体6
.第2面の導体膜4を介して入電部分9と導通している
。つぎに、第7図に示すように、第1面の全面にマスク
12を形成し、第8図に示すように、第2面のパターン
となる部分にレジスト13を形成して、エツチングを行
なったのち、マスク12.レジスト13を除去して、第
2面にパターンを形成すれば9部分8aにのみメッキが
施されたプリント基板が完成する。
In this case, the portion 8a to be plated is the pattern 8° conductor 6.
.. It is electrically connected to the current input portion 9 via the conductor film 4 on the second surface. Next, as shown in FIG. 7, a mask 12 is formed on the entire surface of the first surface, and as shown in FIG. 8, a resist 13 is formed on the part that will become the pattern on the second surface, and etching is performed. Later, mask 12. By removing the resist 13 and forming a pattern on the second surface, a printed circuit board in which only nine portions 8a are plated is completed.

以上説明したように、この発明に係るプリント基板のメ
ッキ方法においては、ツクターンの一部にしかもプリン
ト基板の中央部のノくターンのみにメッキを施すことが
できるので、たとえば金メッキなどの場合には、パター
ンの必要な部分にのみ金メッキを施すことができるから
、コストが非常に安価である。また、パターンを形成し
たのちにメッキを施すから、メッキのオーバーハングが
生ずることがないので、ブリッジ等の事故が生ずるおそ
れがない。さらに、パターンのエツチングサイド面にも
メッキが施されるので、パターンが腐食されることがな
く9品質が安定している。また。
As explained above, in the printed circuit board plating method according to the present invention, it is possible to plate only a part of the turn and only the center turn of the printed circuit board, so for example, in the case of gold plating, etc. Since gold plating can be applied only to the necessary parts of the pattern, the cost is very low. Furthermore, since the plating is applied after forming the pattern, overhang of the plating does not occur, so there is no risk of accidents such as bridging. Furthermore, since the etched side surfaces of the pattern are also plated, the pattern is not corroded and the quality is stable. Also.

電解メッキによりメッキを施すので、メッキの厚さを自
由に制御することができる。このように。
Since plating is performed by electrolytic plating, the thickness of the plating can be freely controlled. in this way.

この発明の効果は顕著である。The effects of this invention are remarkable.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のプリント基板のメッキ方法の説明図、第
2図ないし第8図はこの発明に係るプリント基板のメッ
キ方法の説明図である。 4・・・導体膜     5・・・スルホール6・・・
導体      7・・・基板8 ・・・ ノく タ 
− ン 8a・・パターン8のメッキを施す部分9・・・入電部
分 10〜12・・・マスク 16・・・レジスト 代理人弁理士 中村純之助 1F1図 才2図 1’3図 才4図 才5図 1−7図 2
FIG. 1 is an explanatory diagram of a conventional printed circuit board plating method, and FIGS. 2 to 8 are explanatory diagrams of a printed circuit board plating method according to the present invention. 4... Conductor film 5... Through hole 6...
Conductor 7... Board 8... Nokuta
- Plating part 8a of pattern 8 9... Power input part 10 to 12... Mask 16... Resist agent Junnosuke Nakamura 1F1 Figure 2 Figure 1'3 Figure 4 Figure 5 Figure 1-7Figure 2

Claims (1)

【特許請求の範囲】[Claims] 両面に導体膜が形成され、上記両面の導体膜がスルホー
ルの内面に設けられた導体によって導通された基板の第
1面にのみパターンを形成し、つぎに上記パターンのメ
ッキを施す部分を残して上記第1面にマスクを形成する
とともに、上記基板の第2面にマスクを形成して、電解
メッキを行ない、上記パターンのメッキを施す部分にメ
ッキを施し、つぎに上記第1面の全面にマスクを形成し
て、上記第2面にパターンを形成することを特徴とする
プリント基板のメッキ方法。
A conductor film is formed on both sides, and a pattern is formed only on the first side of the substrate where the conductor films on both sides are electrically connected by the conductor provided on the inner surface of the through hole, and then the part where the pattern is plated is left. A mask is formed on the first surface, and a mask is formed on the second surface of the substrate, electrolytic plating is performed, and the portions of the pattern to be plated are plated, and then the entire surface of the first surface is plated. A method for plating a printed circuit board, comprising forming a mask to form a pattern on the second surface.
JP12402081A 1981-08-10 1981-08-10 Printed circuit board plating method Expired JPS5952556B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12402081A JPS5952556B2 (en) 1981-08-10 1981-08-10 Printed circuit board plating method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12402081A JPS5952556B2 (en) 1981-08-10 1981-08-10 Printed circuit board plating method

Publications (2)

Publication Number Publication Date
JPS5827392A true JPS5827392A (en) 1983-02-18
JPS5952556B2 JPS5952556B2 (en) 1984-12-20

Family

ID=14875036

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12402081A Expired JPS5952556B2 (en) 1981-08-10 1981-08-10 Printed circuit board plating method

Country Status (1)

Country Link
JP (1) JPS5952556B2 (en)

Also Published As

Publication number Publication date
JPS5952556B2 (en) 1984-12-20

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