JPS5825261A - Manufacture of semiconductor ic device - Google Patents

Abstract

PURPOSE:To reduce a parasitic capacity between electrodes and impurity layers and thereby to obtain a device of high integration by forming first a large first electrode, making an impurity region by using this electrode as a mask, removing later a part of the first electrode, and providing a second electrode in the place from which the part is removed. CONSTITUTION:One main surface of an Si substrate 5 is covered with a thick oxide film 18, a gate oxide film 19 is formed selectively in a prescribed region, and a poly-Si gate electrode (the first electrode) 13 of a transistor Q3 is provided thereon. The oxide film 19 is etched by using the electrode 13 as a mask, impurity layers 3' and 4' are made thereon, thermal oxidation is applied, and thereby the electrode 13 and the layers 3' and 4' are covered with an oxide film 14. Next, a part of the electrode 13 is removed by etching so as to open the surface 20 of the channel part of the transistor Q3. Then, a gate oxide film 21 is made to grow in an opening part 20 by thermal oxidation, the remaining side surface of the electrode 13 is covered with an oxide film, and an Al gate electrode (the second electrode) 12 is provided. According to this constitution, an impurity laver between the serial connection elements Q2 and Q3 of a three- element memory cell is unnecessitated, and thereby an area occupied therby is reduced, while a parasitic capacity between the electrodes and the impurity layers is also reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor integrated circuit device OII, and particularly relates to a method for manufacturing a structure OII of a series transistor.

Semiconductor memory has been recognized for a long time to be superior in terms of performance due to its ability to be highly adaptable compared to conventional core memory. He was giving up a step. However, X
With the advancement of 5HX technology, the integration density per chip has increased dramatically, and as a result, the cost has developed to 119, which is enough to compete with the core memory of the 4th generation chip.

The present invention is based on the basic trend that higher density increases the usability of the cell as described above, and the nine-point O structure 41K realizes a small size without affecting the function of the cell. The purpose is to provide an effective bottle manufacturing method for obtaining a series transistor structure.

Traditionally, the series transistor structure was
Saaxl-kai@ is showing off. However, this structure is -w
Since the north region is not formed between the gate electrode of E1 and the self-aligning pot, O parasitic capacitance between the gate electrode and the gate electrode becomes a problem, and sufficient density cannot be achieved. A self-aligned 9-space region is formed near one end of the semiconductor substrate II using the @lO gate electrode as a mask.
When an impurity of a reverse conductive layer is introduced into the gate electrode, a drain region is also formed near the other end of the first gate electrode.

This is because a predetermined series transistor structure cannot therefore be obtained.

Therefore, the features of the present invention are as follows: - forming a thin insulating layer on a predetermined surface area of a conductive semiconductor substrate; forming a first electrode in shape on the thin insulating film; A step 1 for introducing impurities of the reverse conductive layer into the semiconductor substrate 1 as a mask, a step of removing a part of the first electrode, and a step of forming a thermal oxide film tube on the surface of the remaining tenth electrode. With the process.

A second electrode is located including the area where the tenth electrode has been removed, and is in contact with the first electrode that remains through the thermal oxide film.
A method of manufacturing a semiconductor integrated circuit device includes step 1 of forming a 0 electrode.

In this way, the present invention first forms the tenth electrode manually, uses this as a mask to form the impurity region, and then removes a part of the first electrode, and this removed portion K11.
Based on the new idea of forming an IO electrode.

? If such a method is used, the parasitic capacitance between the electrode, the impurity region, and 0 can be reduced, and a highly integrated device can be obtained.

Next, an example of a semiconductor integrated circuit device to which the present invention is applied will be explained.

FIG. 1 is a circuit diagram of a three-element cell), write transistor Q1. Read transistor q, information storage transistor q, write, read transistor Q
* # Qa is the write address line for that gate.
, are connected to the read address line 2 and driven thereby. Information is supplied as a charge to the gate electrode of transistor Qs via the digit line and transistor Ql. After the transistor q1 is turned off, the memory content is determined by whether or not there is a charge on the gate electrode of the transistor q, which is reflected in whether the transistor q1 is on or off. Readout is done by turning on the transistor Qv), digit line table transistor Qv
It is detected by whether or not current flows through and q.

In other words, if a charge is applied to the gate of transistor q through transistor q during writing, transistor Q is kept in the on state, so when transistor q is turned on during reading, digit line 3 - transistor q is turned on. Current flows through -Q-. On the other hand, this current will not flow unless charge is applied to the gate of transistor Q through transistor q during writing.Therefore, it depends on whether this current -IIX#l is generated or not.
The memory output of OJ is obtained.

The 3-element dyna-based memory operates in this way, but the second @ is designed to mimic this 3-element dyna-based memory.
3 shows a plan view, and FIG. 3B is a sectional view taken along the line X-X' in FIG.

The ground electrode number and digit line 3 shown in FIG.
and 3', and the writing address line 1' and the reading address line 3' are constructed of aluminum ζ wires. The gate electrodes of the transistors Qs * Qv * Ql O are 11 and 12.13, respectively, that is, the transistors q and O
Gate electrode I'll is formed integrally with address $27, and gate electrode 12 of transistor Qv is formed integrally with read address line 2'.

The gate electrode 13 of transistor q is a transistor ship.
It is connected to the source region 6 of . The source region of the transistor q also serves as a diffusion region 4' formed as a ground electrode, which is formed on the surface and connected to the ground conductor O1.
- Because it is connected to the um electric wire.

Usually done. In the conventional configuration, transistors Kai and Q
Since it is required for series connection, the size of the memory tank is determined by its dimensions. That is, the sum of the length in the direction connecting regions 3' and 4' of the gate electrode portions 4xg and xs of the transistors Q*-Qa and the dimension separating the gate electrodes 1m and 13t (digital) II! The distance between S' and ground number 1' is determined), which determines the size S of the memory cell.

Next, an example in which the present invention is applied is shown in FIGS. s is omitted, and the gate electrodes are arranged in parallel with each other with an insulating layer interposed between them, thus forming a transistor Q* s Qs
The aim is to reduce the area occupied by the

FIG. 3 shows a case where the circuit is applied to the circuit of FIG. 1.

In the figure, M is a plan view, and B is a sectional view. Wiring width.

The spacing etc. are the same as in Figure 2.

31st EliilCJiP single crystal semiconductor base 1 [15
A diffusion region 3' and a diffusion region 3' of a conductivity type opposite to that of the ζO semiconductor substrate 6 are provided facing one surface of the ζO semiconductor substrate 6. This diffusion region 3'
and 4' correspond to the digit line and ground electrode described above. A gate insulating layer 19 having a required thickness is deposited on the base @SO plane between the diffusion regions 3' and 4', and the diffusion regions 3' and 4' are formed on the upper surface of the gate insulating layer 19. The gate electrodes 12 and 15 are insulated in parallel in the direction connecting the 1
It's true. The gate electrode 12 is formed of aluminum 52,
This is used as the gate electrode of the transistor q, and the gate electrode 13 is made of polycrystalline silicon, for example, and is used as the gate electrode of the transistor Qvf).

ζO In FIG. 5, a transistor CpsO gate electrode 13 is first formed of polycrystalline silicon on a gate insulating layer 19, and an oxide film 14 is formed on the gate electrode 13 by, for example, thermal oxidation or anodic oxidation. After that, the gate electrode 1m of the transistor is formed using aluminum. In this case, the aluminum electrode 1m can be formed so that a part thereof overlaps with the gate electrode Is. With such an overlapping portion, even if the formation position of one gate electrode 1 is shifted slightly, there will be no gap between the gate electrode 18 and IIs that is more than the thickness of the oxide film 140, and both gate electrodes 1 150rR can be formed as close as possible while maintaining insulation.

ζO, the transistor Qs has the diffusion region S' as the drain and the electrode 13 as the gate electrode, and the transistor Qs has the drain as the diffusion region S' and the electrode 15 as the gate electrode.

In this way, two transistors Q* connected in series with each other
By omitting the diffusion regions corresponding to both ends of the common LaO, as a result, the area of the cell O is reduced by about half by 11 mK, as is clear from the comparison with Part 1.

Next, an embodiment of the present invention will be explained using tube No. 4m.

First, as shown in the fourth II, one side 0 of the single crystal semiconductor substrate 6 is
11t*Ifl covered with a thick oxide film 18, and then removed the region O oxide film 18 that saturates the source, drain, and channel portions of the transistor, and deposited a gate oxide film 18 on this part.
grow. Damn it all 11K) Langista q
, in order to grow polycrystalline silicon for the gate electrode, that is, the first electrode, and form it into a predetermined electrode ISO shape.

Next, as shown in FIG. 4BK, the polysilicon electrode 1s is etched and the oxide film 19 is etched to form impurity regions 8' and 4'.
Create.

Next, as shown in No. 4110, the surfaces of the polysilicon electrode 1s and the diffusion impurity regions S' and 4' are coated with an oxide film 1 by thermal oxidation.
Cover with 4.

Next, as shown in No. 4111DK, a part of the 10th conductor 180 is removed using a photoresist method, and an opening is opened on both sides of the base I, which will become the channel part of the transistor. Finally, by thermal oxidation, a gate oxide film is formed in the opening (llm6), and then a thermal oxide film is formed on the surface of the remaining metal (b) on the first electrode IsO side, and on top of that, the gate electrode 1 is formed by aluminum (R&R). A third electrode is provided to complete the fabrication.

[Brief explanation of the drawing]

The No. LIE is a circuit (2) showing an S-element memory cell. The third garden is an example of the S element 497 rules. Part S■ was created based on the original Il0II example) and 9S
There are 0,000 element memory cells and a new image. Fourth!
Il is Shinsokaku, which shows an example of the present invention. Qs t Qs: Transistor connected in series. 5: Single crystal semiconductor substrate, 5', 4/@diffusion region, 1m
. 13: Gate electrode, 19: Gate insulating layer. 1 kaya v-2 days

Claims (1)

[Claims] One type of process involves forming a thin insulating film on a predetermined surface area of a conductive semiconductor substrate, the other type involves forming a first electrode in shape on a wrinkled insulating film, and the process type forms a thin insulating film on a predetermined surface area of a conductive semiconductor substrate. 1. Step of introducing impurity of K reverse conductivity, step of removing part of the first electrode, and step of removing the remaining electrode 6.
A second electrode is formed on the remaining 14D electrode via the thermal oxide film, which is located including the area where the 10th electrode has been removed, and which is located at a position including the area where the 10th electrode has been removed. 1. A method for manufacturing a semiconductor integrated circuit device, comprising: forming a semiconductor integrated circuit device.