JPS5822887B2 - Zetsuen Gate Transistor Omochiitasyutsuryoku Waro - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an output circuit that uses insulated gate transistors and obtains an output signal having an opposite phase to an input signal.Generally, when a certain logic gate is connected to the input terminal of a large number of logic gates, that is, when a logic gate is connected to an input terminal of a large number of logic gates, When there are many outputs, the load capacity increases, and a push-pull type buffer output circuit is often used to drive such a large load capacity.

Conventionally, this circuit has been composed only of enhancement type insulated gate transistors.

FIG. 1 shows a conventional output circuit of this type for obtaining an output signal having a phase opposite to that of an input signal.

1 and 2 are first and second N-channel enhancement type insulated gate transistors connected in series between the power supply terminal 3 and the ground, and the drain of the first transistor 1 and the source of the second transistor 2 are connected in series. The midpoint of the connection is connected to the output terminal 4, while the input terminal 5 is connected directly to the gate of the transistor 1 of the box 1 and to the gate of the second transistor 2 via an invercro.

7 is the load capacity. When the signal applied to the input terminal 5 changes from a high potential to a low potential, the first and second transistors 1 and 2 turn off and on, respectively, and the load capacitance 7 is reduced by the current flowing through the second transistor 2. When charged, a high potential signal appears at the output terminal 4, and conversely, when the signal applied to the input terminal 5 changes from low potential to high potential, the first
The second transistors 1 and 2 are turned on and off, respectively, and the charge in the load capacitor 7 is discharged through the first transistor 1, so that a low potential signal appears at the output terminal 4.

However, in the conventional circuit described above, excessive customization occurs due to charging and discharging of the load capacitor 7, that is, the responsiveness of the output signal to the input signal is quite poor.

The present invention is intended to improve this excessive customization, and is characterized in that at least the first transistor 1 is constructed of a depletion type or an enhancement type with a threshold voltage close to O■.

2A and 2B show the first and second embodiments of the present invention, respectively,
In each of the first and second embodiments, the first transistors 8A and 8B on the ground side are both depletion type N-channel insulated gate type transistors, and the second transistor 9A on the power side.

9B is enhancement type and depression type N respectively.
It is a channel insulated gate transistor.

The other parts in each embodiment are the same as Yang Cheng in FIG.

In each of the first and second embodiments, when the input signal shown in FIG. 3A is applied to the input terminal 5, the input signal shown in FIGS.
The output signal is obtained.

The thin line in FIG. 3 indicates a custom-made product similar to the conventional example shown in FIG.

That is, in the first embodiment, the falling characteristic is improved, and in the second embodiment, both the rising and falling characteristics are improved.

Next, to further explain the improvement effect using specific numerical values, first, the general % I'IE of an insulated gate transistor will be described.

Now, let the potentials of the source, drain, and gate of this transistor be ■s, VD, and ■, respectively, and let the threshold voltage be "" and the current amplification factor be β, then VD≧V, -■
When r+ Vs, the transistor is in the saturation region, and the source at that time.

The drain current Is is 1, . 1 (1) −・−Is−, β(Vo−Vr Vs)2 When VD<■−■r10■s, the transistor is in the unsaturated region, and the source and drain currents at that time are , ■9−■5 (2)・・・・・・■−β(VC+=vs %
2)・(VDVS).

Now, in Figures 1 and 2, the value of β for all transistors is lXl0-3 (AV''), Vr for all enhancement type transistors is 1.5■, and for all depletion type transistors By setting vT to -1.5V and further setting the voltage of the power supply terminal 3 to 5V, a comparison of excessive customization between the conventional example and the first and second embodiments will be made.

The low potential of the input signal shown in Figure 3A is 0■, and the high potential is 8
1 and 2, this signal is inverted after passing through the inverter 6, and its high potential is 8■ and its low potential is 1■.

In the first embodiment, when considering the transient characteristics after the input signal changes from a low potential to a high potential, attention will be paid to an arbitrary state in which the charge voltage of the load capacitor 7 is 4.

At this time, the second transistor 9A is in an off state, and the first transistor 8A is vo-8Vl, vs=O
It is in a saturated conduction state at V, VD = 4 V.

Therefore, when the above equation (2) is applied to the first transistor 8A, the current flowing through the transistor becomes 30 mA.

All of this current becomes a discharge current of the load capacitor 7.

On the other hand, if we focus on the same transient state in the conventional example shown in Figure 1,
At this time, the first transistor 1 has ■G=8V, VS=O
V, VD - is in an unsaturated conducting state at -4V, and the second transistor 2 is l vo - I V , VS = 4-
It is in the off state at V.

Therefore, when the above equation 2 is applied to the first transistor 1, the current flowing through the transistor becomes 18 mA.

All of this current becomes a discharge current of the load capacitor 7.

Therefore, in the first embodiment, the discharge current is 67 times more than that of the conventional example, and the falling characteristic is improved.

In the second embodiment, considering excessive customization after the input signal changes from high potential to low potential, as an arbitrary state,
Note that the load capacitor 7 is charged to 1V.

At this time, the second transistor 9B is ■G-8■, v
It is in an unsaturated conductive state at s-1■ and VD-5■.

Therefore, when the above equation (2) is applied to the second transistor 9B, the current flowing through the transistor becomes 26 mA.

On the other hand, transistor 8B of solution 1 is VG-OV t VS
= OV, VD -1■ is in unsaturated conduction state,
When the above equation (2) is applied to the first transistor 8B, the current flowing through the transistor becomes 1-mA, and therefore the charging current of the load capacitor 7 becomes 25 mA.

On the other hand, if we pay attention to the same transient state in the conventional example shown in FIG. 1, at this time the first transistor (1) is in the off state, and the second transistor (2) is at 1G-8V.

■It is in an unsaturated conductive state at s-1■ and VD-5■.

Therefore, the above formula (2) for the second transistor (2)
When applying , the current flowing through the transistor is 14mA
becomes.

Therefore, in the second embodiment, compared to the conventional example, 78% more charging current flows and the customization is improved.

When the charging voltage of the surface load capacitor 7 exceeds 15V, the first transistor 8B enters a saturated state, but the current at that time is about 1.1 mA according to the above equation (1), so there is no effect.

In addition, in the second embodiment, when considering excessive customization after the input signal changes from a low potential to a high potential, pay attention to the state where the charging voltage of the load capacitor 7 is 4■ as an arbitrary state. do.

At this time, the second transistor 9B is VG-1■, ■5-
4V and is in the off state, and the first transistor 8B is at VG.
-8V, Vs=OV.

In the unsaturated conduction state at VD=4 V, a current of 30 mA flows through the first transistor 8B as in the first embodiment, and in the second embodiment, the discharge is 67 times more than in the conventional example. The current flows and the falling characteristics are improved.

When the charging voltage of the surface load capacitor 7 becomes 2.5V or less, the second transistor 9B is also turned on, and the transistor becomes saturated, but as can be seen from the above equation (1), the current is 3 m at maximum.
Since it is grade A, there is no impact.

In the above embodiments, the present invention is also applicable even if each transistor is a P-channel type.

Further, in the above embodiment, at least the first transistor is of the depletion type, but the same effect can be obtained even if this is changed to an enhancement type with a threshold voltage close to O■.

As is clear from the above description, the present invention utilizes the feature that current easily flows, which is the characteristic of depletion type or enhancement type with threshold voltage close to O■, and uses an insulated gate transistor to generate a signal with a phase opposite to that of the input signal. This improves the responsiveness of an output circuit that obtains an output signal.

[Brief explanation of drawings]

□ FIG. 1 is a conventional circuit diagram, FIGS. 2A and 2B are circuit diagrams of first and second embodiments of the present invention, respectively, and FIG. 3 is a waveform diagram for explaining the present invention. 1j2j9A...Enhancement type transistor, 8A, 8B, 9B...Depression type transistor.

Claims (1)

[Claims] 1. A first insulated gate transistor is connected to the ground side, and a second insulated gate transistor is connected to the power terminal side in series with the first transistor, and the first and second
In an output circuit, an output signal having an opposite phase to the input signal is extracted from the connection midpoint of the first and second transistors by applying the input signals in a complementary relationship to each of the gates of the transistors. The connection is such that the input is directly input to the first transistor, and the input is input to the second transistor via an inverter, and at least the first transistor is a depletion type or an enhancement type with a threshold voltage close to O■. An output circuit using an insulated gate transistor characterized by: