JPS58224496A - Method for writing data in ram - Google Patents

Abstract

PURPOSE:To rewrite only a specified bit among plural bits temporally stored to attain rewriting by connecting a capacitor for temporally storing to each data terminal of an RAM. CONSTITUTION:Prescribed address and writing content changing address are applied to the address input terminals A0-A9 of the RAM1 and the address input terminals A10-A12 of a decoder 2 respectively. The stored content of the address appeares to the data terminals of the RAM1 and logic 1 or 0 stored in capacitors 4-0-4-7 corresponding to respective addresses. A write pulse is applied to a terminal T1 and internal impedance observed from the data terminal of the RAM1 is increased. In the decoder 2, only a buffer corresponding to a required bit is turned on among buffers 5-0-5-7, so that only the corresponding capacitor is rewritten by a write data input applied from a terminal T2. When the impression of write pulse is released, the contents of the capacitors 4-0-4-7 are written in the RAM1 again.

Description

[Detailed description of the invention] Regarding AM writing method.

In this type of conventional RAM, when the writing unit is composed of two or more bits, data must be written in bits through a central processing unit (CPU). for that.

It has the disadvantage that it takes time to write. Therefore, in order to prevent the writing time from increasing.

If you want to write in focus units without going through OP tJ, you will have to use an RA where the write unit is 1 bit,
I was in an inconvenient situation where I had no choice but to use M.

An object of the present invention is to provide a capacitor for temporary storage at each data terminal of the RAM, so that only a specific bit can be rewritten from among the multiple bits temporarily stored during writing without going through the CPU. RA whose write unit consists of at least 2 bits.
M writing method is provided.

According to the invention, RA consisting of at least 2 bits
In M, a capacitor is connected to each of the data terminals of RA and M, and when writing to the RAM in bit units, the bit contents that have already been written are temporarily stored in each of the capacitors, and these capacitors are After rewriting only the corresponding bits among the bits stored in .

A RAM writing method characterized by rewriting is obtained.

Next, a RAM writing method according to the present invention will be described by way of an embodiment with reference to the drawings.

FIG. 1 illustrates the configuration of an embodiment according to the present invention. In this example, 1 is a RAM composed of 8 bits per word, 2 is a decoder having 3 to 8 input/output terminals, and 6 is a data selector having 8 to 1 input/output terminals. and.

Data input/output terminal of RA1v'll. -D7 has 4-
Capacitors fl to 4-7 are connected correspondingly. 5-0 to 5-7 are tri-state buffers, which are selectively controlled by the output of the decoder 2, and input write data to capacitors 4-0 to 4.
-7 to the corresponding capacitor and used to rewrite its contents. Data selector 3 is RAM
When receiving the output read from 1, it selects it according to the address input and outputs it as data.

In the above configuration, to explain the data pasting operation of RA'M1, first, a predetermined address is input to the address input terminals Ao, , , , A, of RA, M i, and the address input of the decoder 2 is Terminal A10゜AI
Give the address for changing the written content to I, AI□. As a result, after the access time has passed, 1'(
AMl data terminal. The stored contents of the address appear at -D7, and the logic "I 11+" or "OI+" is stored in the respective corresponding capacitors Co-07.

Subsequently, a sliding pulse is applied to terminal 1-1, and RA
M1 terminal. ~1] Increase the internal impedance seen from 7. In addition, the input side of data selector B and the output side of buffers 5-0 to 5-7 are connected to capacitor 4-
This is because it is in a high impedance state with respect to 0 to 4-7.

The charge stored in the capacitor is retained. At the same time, while the write pulse is applied to the terminal T1, the decoder 2 reads the buffers 5-0 to 5-7.
Since only the buffer corresponding to the desired bit is controlled to be "on", only the capacitor for the corresponding one bit is rewritten as new data by the write data input from terminal T2.Others Since the contents of the capacitors 4-0 to 4-7 retain the data before the write pulse control, as a first step, by removing the application of the write pulse, the capacitors 4-0 to 4-7 contain the newly rewritten data. The contents of are all T(A, 1v
11 is written again.

FIG. 2 is a block diagram showing the structure of an 8-bit parity storage device as an application example of the RAM writing method according to the present invention. In this figure, 9,1
1 to 19 are RAMs with 8 bits per word, and 20 is the first RAM.
In the example shown in the figure, components excluding T(A, lvi) are shown.

21 is an entry/exit cover sofa, and 22 is an external bus.

In this example, since RAM 19 can be used for parity bits and the same 1-word 4-8 bit RA and M can be used as other RAMs 11 to 18, Pi A
If you make the connection pins of M compatible.

If necessary, it can be freely replaced as an EP ROM. This allows the memory to be converted to R without changing the 8 circuits.
An economical storage device with parity bits that can be used for both OM and RAM is obtained.

As is clear from the explanation given below, according to the present invention, a capacitor is provided for each data terminal of the RAM for temporary storage, and the data stored in each of these capacitors is
By rewriting specific bits from among the bit contents, a RAM whose write unit is 2 or more bits can be created.
In addition, it is possible to easily write data in bits without going through the CPU, which takes time for writing processing, and it can also be used as both ROM and RAM in storage devices with parity bits that use a large number of memories. To the extent that it is possible, the effect obtained is to improve performance and economy.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an embodiment according to the present invention. FIG. 2 is a block diagram showing the structure of a storage device with a parity bit as an application example of the RAM write method according to the present invention. In the figure, 1.11 to 19 are RAM, 2 is a decoder,
3 is a data selector, 4-θ to 4-7 are capacitors, 5
-0 to 5-7 are tri-state buffers, 20 is the first
In the figure, the components other than the RAM are an input/output vanofer 21 and an external bus 22.

Claims (1)

[Claims] 1. In a RAM composed of at least two humans,
Connect a capacitor to each data terminal of the RAlvi,
When writing to the RAM in bit units, the contents of the bits that have already been written are temporarily stored in the respective capacitors, and only the corresponding bits among the bits stored in these capacitors are rewritten. A RAM writing method characterized by writing.