JPS58222545A - Semiconductor package - Google Patents

Semiconductor package

Info

Publication number
JPS58222545A
JPS58222545A JP10595782A JP10595782A JPS58222545A JP S58222545 A JPS58222545 A JP S58222545A JP 10595782 A JP10595782 A JP 10595782A JP 10595782 A JP10595782 A JP 10595782A JP S58222545 A JPS58222545 A JP S58222545A
Authority
JP
Japan
Prior art keywords
region
sealing
cap
width
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10595782A
Other languages
Japanese (ja)
Inventor
Isamu Kitahiro
北広　勇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP10595782A priority Critical patent/JPS58222545A/en
Publication of JPS58222545A publication Critical patent/JPS58222545A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)

Abstract

PURPOSE:To raise a temperature of region where it is directly related to the sealing and keep the other region as low as possible and thereby suppress the deterioration of semiconductor device as much as possible by providing a region where heat or light is absorbed only in the periphery of the cap of package and by making the width of such region almost equal to the width of sealing material. CONSTITUTION:31 is the central portion of sealing cap and 32 is the graphitized region in the periphery of cap 31. The surface of region 31 is applied by a heat resistant paint or roughly finished by sand blast etc. The processed cap 6 and soldering material 5 are stacked on the package 1 and it is sealed by putting it into the conveyor furnace. Since the region 32 is graphitized or finished roughly, it absorbs efficiently heat and light and thereby the soldering material 5 flows smoothly. Even when a resin adhesive material is used in place of the soldering material 5, the temperature of region 32 first rises and thereby perfect sealing effect can be obtained. Moreover, the region 32 is formed in the periphery of the cap and the width is set almost equal to the width of the brazing material, soldering material and resin sealing material. Thereby, only the temperature of the sealing area can be raised effectively and influence on internal elements and deterioration thereof can be lessened.

Description

【発明の詳細な説明】 本発明は半導体デバイスを収納した半導体収納容器に関
するものであり、半田材又は樹脂接着材等の封止材の溶
融部分のみを効率的に加熱しうる構造を提供するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor storage container housing a semiconductor device, and provides a structure that can efficiently heat only the melted portion of a sealing material such as a solder material or a resin adhesive. It is.

一般に半導体デバイスを中空パッケージに気密封止する
方法として、金属キャップを用いた抵抗溶接、半田材等
を介しての封止、樹脂接着剤による封止がある。第１図
に半田材を介して封止する場合の構成を示す。第１図は
セラミック・パッケージの例を示し、１はＬＳＩ収納容
器本体のセラミックパッケージ、２はＬＳＩ（大規模半
導体集積回路）、３は金属細線、４は封止部すなわち半
田封止用の印刷金属部で通常金メッキされている。Generally, methods for hermetically sealing a semiconductor device in a hollow package include resistance welding using a metal cap, sealing via a solder material, and sealing using a resin adhesive. FIG. 1 shows a configuration in the case of sealing via a solder material. Figure 1 shows an example of a ceramic package, where 1 is a ceramic package for the main body of an LSI storage container, 2 is an LSI (large-scale semiconductor integrated circuit), 3 is a thin metal wire, and 4 is a sealing part, that is, printing for solder sealing. The metal part is usually gold plated.

６は額縁状の半田材で一般に金−錫又は鉛−錫等の合金
が使われる。６は金属薄板で金メッキされている。Reference numeral 6 is a frame-shaped solder material, which is generally made of an alloy such as gold-tin or lead-tin. 6 is a thin metal plate plated with gold.

封止するには、以上述べたセラミックパッケージ１と半
田材６と金属薄板６を一致させて適度の加重をかけ、コ
ンベア炉を通して半田材を溶かし封止する。このコンベ
ア炉の断面を第２図に示す。For sealing, the above-described ceramic package 1, solder material 6, and thin metal plate 6 are aligned, an appropriate load is applied, and the solder material is melted and sealed through a conveyor furnace. A cross section of this conveyor furnace is shown in FIG.

２１は管で内部にベルト２４が敷かれ、物を運ぶように
できている。２２はヒータ、２３は雰囲気ガス吹き出し
口、２５はパッケージを置く台、２６は第１図のセラミ
ックパッケージ、２７は押えバネである。６は第１図の
金属キップであり、図示してないがその下には半田材６
が敷かれている。封止のだめの温度上昇は主として管２
１の管壁からの輻射熱と雰囲気ガスによる対流熱とによ
っている。こうしたコンベア炉を用いた場合、通常用い
られている金メッキのキャップ６では反射率が大きく、
熱の吸収が不充分なため、必要以上に管壁の温度を上げ
、また雰囲気ガスの流量も上げる必要があった。Reference numeral 21 is a tube with a belt 24 laid inside to carry objects. 22 is a heater, 23 is an atmospheric gas outlet, 25 is a stand on which the package is placed, 26 is the ceramic package shown in FIG. 1, and 27 is a presser spring. 6 is the metal cap shown in Figure 1, and below it is solder material 6 (not shown).
is laid out. The temperature rise in the sealed reservoir is mainly caused by pipe 2.
This is due to radiant heat from the pipe wall of No. 1 and convection heat from the atmospheric gas. When such a conveyor furnace is used, the normally used gold-plated cap 6 has a high reflectance.
Because of insufficient heat absorption, it was necessary to raise the temperature of the tube wall more than necessary and also to increase the flow rate of the atmospheric gas.

そこで本発明は上記問題点を解決し、容易に完全な封止
を可能とする構造を提供するもので、第３図に実施例を
示すとともに以下にその説明を行なう。第３図Ａは本発
明に用いるキャップの一例の上面図、第３図Ｂは封止の
際のセラミックパッケージの構成を示す。３１は封止用
キャップの中央部、３２はキャップ３１の周辺部黒化領
域でこの領域３１の部分は耐熱性塗料を塗布するかもし
くはサンドブラスト等で表面を粗くしても良い。The present invention solves the above-mentioned problems and provides a structure that allows complete sealing with ease. An embodiment is shown in FIG. 3 and will be explained below. FIG. 3A is a top view of an example of the cap used in the present invention, and FIG. 3B shows the structure of the ceramic package during sealing. Reference numeral 31 denotes a central portion of the sealing cap, and 32 denotes a blackened peripheral region of the cap 31. The surface of this region 31 may be coated with a heat-resistant paint or roughened by sandblasting or the like.

なお第３図Ｂの各部に付した番号は、第１図と同一番号
とした。Note that the numbers assigned to each part in FIG. 3B are the same as those in FIG. 1.

このように処理したキャブ６と半田材５をパッケージ１
に重ね、第２図に示すコンベア炉を通すことにより封止
する。この際、本発明では、第３図に示す領域３２が黒
化又は粗面化されているたなる。このことは樹脂封止で
も同様のことが言える。即ち、第３図Ｂの半田材６のが
わりに樹脂接着材を用いても、周辺に比べて領域３２の
温度がまず上昇するため、完全な封止が可能となる。ま
た、領域３２をキャップの周辺部に形成し、その幅をロ
ー材、半田材、樹脂封止材の幅にほぼ等しくしておくと
封止用の部分の温度のみを効果的に上昇させ、内部の素
子に与える影響、その劣化等も少なくできる。The cab 6 and solder material 5 treated in this way are packaged in package 1.
2 and passed through a conveyor furnace as shown in FIG. 2 to seal. At this time, in the present invention, the area 32 shown in FIG. 3 is blackened or roughened. The same can be said for resin sealing. That is, even if a resin adhesive is used instead of the solder material 6 in FIG. 3B, the temperature of the region 32 rises first compared to the surrounding area, so complete sealing is possible. Furthermore, if the region 32 is formed around the periphery of the cap and its width is made approximately equal to the width of the brazing material, solder material, and resin sealing material, the temperature of only the sealing portion can be effectively increased. The influence on internal elements and their deterioration can also be reduced.

以上のように、本発明は半導体収納容器を封止するに際
し、封正に直接関与する領域の温度を高くし、他の領域
の温度は極カ低くシ、半導体デバイスの劣化を極力弁え
ることを可能にするものですぐれた実用的効果を有する
ものである。As described above, when sealing a semiconductor storage container, the present invention increases the temperature of the area directly involved in sealing, and keeps the temperature of other areas extremely low, thereby minimizing deterioration of semiconductor devices. It has excellent practical effects.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は半田封止セラミックパッケージの構造断面図、
第２図はコンベア炉の概略断面図、第３図Ａは本発明の
一実施例のパッケージに用いるキャップの平面図、第３
図Ｂは同パッケージの構造断面図である。 １・・・・・・収納容器（パッケージ）、４・・・・・
・封止部、５・・・・・・封止材、６・・・・・・キャ
ップ、３２−−−−−・熱又は光収納領域。 代理人の氏名　弁理士　中　尾　敏　男　を１か１名第
１図 第２図 ／’（１２にＱ５Figure 1 is a structural cross-sectional view of a solder-sealed ceramic package.
FIG. 2 is a schematic sectional view of a conveyor furnace, FIG. 3A is a plan view of a cap used in a package according to an embodiment of the present invention,
Figure B is a structural sectional view of the same package. 1...Storage container (package), 4...
- Sealing part, 5... Sealing material, 6... Cap, 32 - Heat or light storage area. Name of agent Patent attorney Toshio Nakao 1 or 1 person Figure 1 Figure 2/' (Q5 on 12

Claims (2)

【特許請求の範囲】[Claims] （１）半導体素子を収納するパッケージのキャップの一
主面の少なくとも高辺部に熱又は光を吸収する領域を設
けたことを特徴とする半導体収納容器。(1) A semiconductor storage container characterized in that a heat or light absorbing region is provided on at least the high side of one main surface of a cap of a package for storing a semiconductor element. （２）熱又は光をよく吸収する領域がキャップの周辺部
に限定され、かつその幅が封正に使用する封止材の幅に
ほぼ等しいことを特徴とする特許請求の範囲第１項記載
の半導体収納容器。(2) Claim 1, characterized in that the region that absorbs heat or light well is limited to the periphery of the cap, and the width thereof is approximately equal to the width of the sealing material used for sealing. semiconductor storage container.
JP10595782A 1982-06-18 1982-06-18 Semiconductor package Pending JPS58222545A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10595782A JPS58222545A (en) 1982-06-18 1982-06-18 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10595782A JPS58222545A (en) 1982-06-18 1982-06-18 Semiconductor package

Publications (1)

Publication Number Publication Date
JPS58222545A true JPS58222545A (en) 1983-12-24

Family

ID=14421291

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10595782A Pending JPS58222545A (en) 1982-06-18 1982-06-18 Semiconductor package

Country Status (1)

Country Link
JP (1) JPS58222545A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0511537U (en) * 1991-07-18 1993-02-12 テイーデイーケイ株式会社 Electronic parts

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0511537U (en) * 1991-07-18 1993-02-12 テイーデイーケイ株式会社 Electronic parts

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