JPS5822155Y2 - Oyakoshikidenkidokeinoshuuseishingouhatsuseisouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to a correction signal generating device for correcting instructions in a parent-child electric timepiece in which a child timepiece is driven by a polarized signal from a parent timepiece.

In conventional parent-child electric clocks, pulses of different polarity are alternately sent out from the parent clock every 30 seconds, for example, a negative pulse at 0 seconds of each number, and a positive pulse at each 30 seconds. The child clock is driven by the polarized signal.

If the polarized signal is not transmitted, for example due to a power outage, a malfunction of the master clock, or a fault in the transmission line, and therefore the indication of the slave clock differs from the actual time,
need to fix that.

The correction involves sending out a polarized signal at a much higher speed than the normal polarized signal to advance the hands of the slave clock so that it indicates the correct time.

When the correction signal is generated and stopped, if the correction signal is always sent as a signal of a predetermined width and does not end with a signal of the predetermined width, the pulse width of the correction signal will be If the width is narrower than a predetermined width, the sensitivities of the plurality of child clocks are not necessarily the same, and some of them are driven while others are not, resulting in variations in the instructions among the child clocks.

From this point of view, in the past, a switch was provided to switch between the normal side and the corrected side, and a start switch was also provided to generate a correction signal, and two switches were provided, and when returning from the corrected state to the normal state. If you accidentally switch the changeover switch to the normal side without first turning off the start switch and then returning the changeover switch to the normal side, the width of the final correction signal may vary and the time indication may vary. was there.

That is, two switches were provided, and the order of operation of the switches had to be constant.

Providing two switches in this manner is not desirable because the order of their operations may be incorrect, or one may be forgotten.

From this point of view, this invention uses only one changeover switch, automatically generates a correction signal of a predetermined width, and ends with a correction signal of a predetermined width. An object of the present invention is to provide a correction signal generating device with no variation in instructions.

Next, an example of the correction signal generating device according to this invention will be explained with reference to the drawings.

In Fig. 1, 1 indicates a normal polar signal generation circuit, from one terminal 2 of which a signal 30 is generated as shown in Fig. 2A, and from the other output terminal 3, a signal 4 is generated as shown in Fig. 2B. As shown in the figure, the O〃signal 5 is generated.

These 30 signals are 30 for each issue? ), respectively, and the 0" signal is generated at the time O".

These signals 4 and 5 pass through gates 6 and 7, and further pass through OR gates 8 and 9, respectively, to a polarized signal amplifier 10, whose amplified output is supplied as a polarized signal to terminals 11. 12 to the child clock, for example.

On the other hand, the correction polar signal generation circuit 14 is composed of an astable multivibrator 15 and a circuit 16 that converts its output into a polar signal, and the terminal 30 of the conversion circuit 16 in FIG. 2A from which the signal is obtained. 17 and the terminal 18 from which the O" signal in FIG.
0.

This correction signal has a much shorter cycle than the normal polarized signal.

In this invention, a switch 25 is provided for switching between a normal state and a corrected state.

The fixed contact 26 of the switch 25 is on the normal side, the fixed contact 27 is on the stop position, and the fixed contact 28 is on the correction side.

When the switch 25 is switched from the correction side 28 to the normal side 26, the gates 6.7 and 19.20 are switched after the current correction signal O〃 signal or 30〃 signal ends.

Therefore, the correction side contact 28 of the switch 25 is connected to the OR gate 3.
0 to the drive side of the astable multivibrator 15.

Further, in this example, each signal from the 0 signal output terminal 18 from the polarized correction signal generating circuit 14 and the output terminal 31 obtained in the middle of the circuit 16 is also supplied to the input side of the OR gate 30.

The output side of the OR gate 30 is supplied to the OR gate 32,
This OR gate 32 is the normal contact 2 of the changeover switch 25.
6 is also connected to the input side, and the output is the correction gate 19 and 2.
0 and is also supplied to the normal gates 6 and 7 through the inverter 33.

In this configuration, when the changeover switch 25 is connected to the normal contact 26, the input of the OR gate 32 is low and is 0'', and this is given to the correction gates 19 and 20, so these are useful for correction. The modified signal from the pole signal generation circuit 14 is not supplied to the amplifier 10.

However, the output from the OR gate 32 is given as a high level "1" to the normal gates 6 and 7 through the inverter 33, and these gates are open and the signal from the normal polar signal generation circuit 8 is applied to the normal gates 6 and 7. 7 to the polarized signal amplifier 10, and this normal polarized signal is supplied to the slave clock.

In this state, when the selector switch 25 is switched to the correction side 28 at time ti, a low level "O" is given to the OR circuit 30 through the switch 25 as shown in FIG. 3A, and its output is a high level """1". becomes.

Therefore, the astable multivibrator 15 is driven, and from this, an oscillation pulse as shown in FIG.
Therefore, the 30〃 signal and the 0γ signal shown in FIG. 3F and G are obtained at the terminals 17 and 18.

Note that the outputs shown in FIG. 3C, D, and E are obtained at terminals 35, 31, and 36 in the polar conversion circuit 16.

Further, the high level of the OR gate 30 is applied to the OR gate 32, and its low level output opens the correction gates 19 and 20, and conversely closes the normal gates 6 and 7.

Therefore, the normal signal from the normal polar signal generation circuit 1 is prevented from being supplied to the amplifier 10, and the signal from the correction polar signal generation circuit 14 is supplied to the amplifier 10.

The modified polarized signal from the modified polarized signal generation circuit 14 is the third polarized signal.
As shown in Figure F, the signal is always generated from the 30〃 signal.

The leading edge of the signal at terminal 31 (FIG. 3D) coincides with the leading edge of the 30〃 signal, and its trailing edge coincides with the leading edge of the 0'' signal.

Therefore, even if the selector switch 25 is switched to the normal side in the middle of the signal 30 (for example, as shown at time t2), a low level is applied to the OR gate 30 in the case where each signal from the terminals 18 and 31 ends, and the OR gate 30 (7) The output is at a high level, and the correction gates 19 and 20 are open and the normal gates 6 and 7 are closed.

After switching the switch 25 to the normal side, when the correction OF/signal ends, the OR gate 3 is activated for the first time (time t3).
0 becomes a low level, the output of the OR circuit 32 becomes a high level, the gate N9.20 closes, the normal gates 6 and I open, and a normal polarized signal is supplied to the amplifier 10.

In this way, no matter when the switch 25 is switched from the correction side to the normal side, the correction gates 19 and 20 are closed and the normal gates 6 and 7 are opened only when the correction 0 signal is finished.

Therefore, the switching is always performed after the correction signal has been output correctly, and there is no risk that the instructions of the slave clocks will vary due to switching midway.

Moreover, the operation simply controls one selector switch 25, and there is no need to use two switches.
Moreover, the operation is simple without the need to consider the order of operations, and the number of parts can be reduced.

In the above description, the changeover from correction to normal is always made after the end of the 0〃 signal, but the changeover may be made after the end of the 30〃 signal for correction.

Alternatively, the switching may be made when either the 0〃 signal or the 30〃 signal ends.

In this case, the signal at terminal 31 is not supplied to gate 30, but the signals at terminals 1T and 18 are supplied to gate 30.

[Brief explanation of drawings]

Fig. 1 is a logic circuit diagram showing -fu of the correction signal generator for a parent-child electric clock according to this invention, Fig. 2 is a diagram showing a polarized signal, and Fig. 3 is an output waveform of the polarized signal generator for correction. It is a diagram. 1: Normal polarized signal generator, 6, 7: Normal gate, 10
: Output amplifier, 14: Correction polar signal generator, 19,2
0: Correction gate, 25: Changeover switch, 30.32
Nior Gate, 33: Inverter.

Claims (1)

[Scope of utility model registration request] A switch that switches between a corrected state and a normal state, a corrected polarized signal generation circuit that starts oscillation and generates a corrected polarized signal when the switch is set to the corrected state, and a corrected polarized signal generation circuit that always generates a normal polarized signal. a polarized signal generating circuit; a correction gate circuit that is controlled to open by switching the switch to a correcting state and supplies a correction signal from the corrected polarized signal generating circuit to the polarized signal amplifier; and the switch. a normal gate circuit which is controlled to be open by switching to a normal state and supplies the normal polarized signal of the normal polarized signal generating circuit to the polarized signal amplifier; When the switch returns to the corrected state side and the switch is returned from the corrected state side to the normal state side, the oscillation state of the corrected polarized signal generation circuit is maintained while the corrected polarized signal exists, and the corrected gate A correction signal generating device for a parent-child electric clock, comprising means for keeping the circuit open and a normal gate circuit closed.