JPS6035635B2 - electronic clock - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a drive circuit for a two-phase motor that rotates the hands of an electronic timepiece, and more particularly to an improvement in a drive circuit that can compensate for any second stoppage purely electronically.

In the drive circuit of an electronic clock, various methods have been proposed in which the static position of the rotor immediately before the reset is applied is electronically stored, and pulses are generated so that the first drive pulse applied after the reset is released is not wasted. has been done. As an example, a flip-flop without a reset function, such as a toggle flip-flop, is provided in the latter half of the motor drive signal generating section, and this provides a phase reversal function as well as a function to memorize the magnetic suitability of the motor. can be mentioned.

These methods are excellent in that they do not require mechanical regulation of the stop position of the two-phase motor during reset, so they can reduce the number of mechanical parts and improve operational reliability. There is. Also, as mentioned above, T. F
Using F or providing such a function to the frequency dividing FF at the final stage of the counter is excellent for simplifying the circuit configuration. However, since everything from the oscillator to the motor is connected in series, both have the drawback of being somewhat weak in noise resistance. An object of the present invention is to provide an improved electronic timepiece drive circuit with higher reliability. In order to achieve the above object, the circuit according to the present invention is a two-phase motor drive circuit of a type in which a drive pulse is generated at a motor drive pulse generation terminal before a reset is started and a drive pulse is generated at another terminal within a predetermined time after a reset signal is released. , a frequency dividing circuit, a control circuit connected to the output device of the frequency dividing circuit, a shaping circuit that shapes the output of the control circuit to generate a motor drive pulse, and an input terminal connected to the output end of the shaping circuit. and a storage circuit configured to adjust the phase of the pulse applied to the motor after the reset signal is released by adjusting the output according to the reset signal and the output of the storage circuit. There is.

In a circuit having such a configuration, a signal is fed back from the motor drive pulse output terminal, so that the circuit operates reliably, and the object of the present invention is completely achieved. The present invention will be described in more detail below with reference to the drawings and the like.

FIG. 1 is a circuit diagram showing an embodiment of a drive circuit according to the present invention. FIG. 2 is a time chart for explaining the operation of the circuit. Frequency divider circuit 1 is a circuit that divides the oscillation frequency of a crystal oscillator (not shown), and is a circuit that enters a reset state when terminal 5 of the reset circuit is at a high level, and when the reset is released, the frequency divider is set to start. The control circuit 4 is this frequency divider 4, this frequency divider 1
This circuit transmits the outputs 1-Q and 1-Q of the circuit as is or inverted according to the control input. The detailed operation of this circuit will be described later. The pulse width adjustment circuit 2 is a circuit that shapes the outputs 45 and 46 of the control circuit 4 and supplies them to an input terminal of a motor (not shown). In this pulse width adjustment circuit 2, when the output 45 of the control circuit 4 changes from day to day, the output 46 is transmitted to 21 with a delay of 7 seconds, so a motor drive pulse A with a pulse width of 7 seconds is generated. When 46 changes from day to L, 45 is transmitted to 22 with a delay of 7 seconds, so a motor drive pulse B with a pulse width of 1 second is generated. In other words, when motor drive pulse A is day, motor drive pulse B is always L, and when motor drive pulse B is day, motor drive pulse A is always L', and although both may become L at the same time, There are no two days at the same time. Moreover, at the time of reset, both are L. The memory circuit 3 is composed of a set-reset flip-flop, and when the motor drive pulse A becomes day, 31 becomes day and 32 becomes L, and when the motor drive pulse B becomes day, it becomes 3.
1 is L and 32 is day, and when motor drive pulses A and B are L, this circuit maintains 31 and 32 in the previous state.

Next, the control circuit 4 will be explained.

When the reset signal 5 is L, both 41 and 42 become L,
43 and 44, which are contradictory, are in the previous state (43 is high level and 4
If 4 is low level, transmission gate 4
In order to open circuits 7 and 48 and turn off the power to inverters 49 and 50, 1-Q is transmitted to 45 and 1-Q is transmitted to 46. Further, when 43 is L and 44 is day, transmission gates 47 and 48 are closed and inverters 49 and 50 are turned on, so 1-Q is transmitted to 45 and 1-Q is transmitted to 46. ), the output pulses are generated alternately from the motor drive pulse A and B generation terminals at intervals of t seconds. Next, if the reset terminal 5 becomes day after the motor drive pulse A is generated as in period 6 in FIG.
Since 2 becomes L, 43 becomes day and 44 becomes L.

Subsequently, the transmission gates 47 and 48 are opened, the inverters 49 and 50 are turned off, and the 1-Q
is transmitted, and 1-Q is transmitted to 46, so motor drive pulse B is generated t seconds after the reset signal is released. In addition, when the reset terminal becomes low after the motor drive pulse B is generated as in period 7 in FIG. 2, 41 becomes L,
42 is the day, so 43 is the L, and 44 is the day. Subsequently, the transmission gates 47 and 48 are closed, the inverters 49 and 50 are turned on, 1-Q is transmitted to 45, and 1-Q is transmitted to 46, so that the motor is turned on after t seconds after the reset signal is released. Drive pulse A is generated.
As is clear from the above description, by using the circuit according to the present invention, it is possible to reset to any second.
In other words, the scale that advances after the reset is released will be an odd number for an even number stop and an even number for an odd number stop. Furthermore, since the circuit according to the present invention controls the output pulses by feeding back signals applied to the final output stage, that is, the signals actually applied to the terminals of the motor, it has better noise immunity than the conventional series arrangement. It can be seen that the operation is higher and more stable. Various modifications can be made to the embodiment circuit described in detail above within the scope of the present invention, and the scope of the present invention extends to all of the claims.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the circuit according to the present invention;
The figure is a waveform diagram for explaining the operation of the circuit. 1... Frequency dividing circuit, 2... Pulse width adjustment circuit, 3... Memory circuit, 4... Control circuit, 5...
...Reset terminal. Figure 1 Figure 2

Claims (1)

[Claims] 1 means for generating two divided outputs with different phases in response to a clock signal; means for switching between outputting the two divided outputs directly or via an inverter; first and second output terminals taken out respectively; means for resetting the means for generating the divided output; means for storing the output states of the first and second output terminals at the time of resetting; and the memory. control means for the switching means for switching between direct output and output via an inverter according to the stored content of the switching means, the first or second output immediately before the reset; An electronic timepiece characterized in that, depending on the output of the terminal, the first output is generated from the other output terminal after the reset is canceled.